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[PULL,37/45] target/arm: Treat SCTLR_EL1.M as if it were zero when HCR_EL2.TGE is set

Message ID 20180814181815.23348-38-peter.maydell@linaro.org
State Accepted
Commit 3d0e3080d8b7abcddc038d18e8401861c369c4c1
Headers show
Series target-arm queue | expand

Commit Message

Peter Maydell Aug. 14, 2018, 6:18 p.m. UTC 
One of the required effects of setting HCR_EL2.TGE is that when
SCR_EL3.NS is 1 then SCTLR_EL1.M must behave as if it is zero for
all purposes except direct reads. That is, it effectively disables
the MMU for the NS EL0/EL1 translation regime.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

Message-id: 20180724115950.17316-6-peter.maydell@linaro.org
---
 target/arm/helper.c | 8 ++++++++
 1 file changed, 8 insertions(+)

-- 
2.18.0
diff mbox series

Patch

diff --git a/target/arm/helper.c b/target/arm/helper.c
index 7b438e43a90..62f63e4e5b9 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -8396,6 +8396,14 @@  static inline bool regime_translation_disabled(CPUARMState *env,
     if (mmu_idx == ARMMMUIdx_S2NS) {
         return (env->cp15.hcr_el2 & HCR_VM) == 0;
     }
+
+    if (env->cp15.hcr_el2 & HCR_TGE) {
+        /* TGE means that NS EL0/1 act as if SCTLR_EL1.M is zero */
+        if (!regime_is_secure(env, mmu_idx) && regime_el(env, mmu_idx) == 1) {
+            return true;
+        }
+    }
+
     return (regime_sctlr(env, mmu_idx) & SCTLR_M) == 0;
 }