diff mbox series

[PULL,30/37] target/arm: Add SCR_EL3 bits up to ARMv8.5

Message ID 20181213145445.17935-31-peter.maydell@linaro.org
State Accepted
Commit 99f8f86d365701fad695be606266aa7dac97ca1c
Headers show
Series target-arm queue | expand

Commit Message

Peter Maydell Dec. 13, 2018, 2:54 p.m. UTC 
From: Richard Henderson <richard.henderson@linaro.org>


Post v8.4 bits taken from SysReg_v85_xml-00bet8.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

Message-id: 20181203203839.757-4-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

---
 target/arm/cpu.h | 10 ++++++++++
 1 file changed, 10 insertions(+)

-- 
2.19.2
diff mbox series

Patch

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 79d58978f7c..20d97b66def 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -1302,6 +1302,16 @@  static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
 #define SCR_ST                (1U << 11)
 #define SCR_TWI               (1U << 12)
 #define SCR_TWE               (1U << 13)
+#define SCR_TLOR              (1U << 14)
+#define SCR_TERR              (1U << 15)
+#define SCR_APK               (1U << 16)
+#define SCR_API               (1U << 17)
+#define SCR_EEL2              (1U << 18)
+#define SCR_EASE              (1U << 19)
+#define SCR_NMEA              (1U << 20)
+#define SCR_FIEN              (1U << 21)
+#define SCR_ENSCXT            (1U << 25)
+#define SCR_ATA               (1U << 26)
 #define SCR_AARCH32_MASK      (0x3fff & ~(SCR_RW | SCR_ST))
 #define SCR_AARCH64_MASK      (0x3fff & ~SCR_NET)