diff mbox series

[09/13] target/arm: Implement ARMv8.1-PMU extension

Message ID 20200211173726.22541-10-peter.maydell@linaro.org
State Superseded
Headers show
Series arm: Implement ARMv8.1-PMU and ARMv8.4-PMU | expand

Commit Message

Peter Maydell Feb. 11, 2020, 5:37 p.m. UTC 
The ARMv8.1-PMU extension requires:
 * the evtCount field in PMETYPER<n>_EL0 is 16 bits, not 10
 * MDCR_EL2.HPMD allows event counting to be disabled at EL2
 * two new required events, STALL_FRONTEND and STALL_BACKEND
 * ID register bits in ID_AA64DFR0_EL1 and ID_DFR0

We already implement the 16-bit evtCount field and the
HPMD bit, so all that is missing is the two new events:
  STALL_FRONTEND
   "counts every cycle counted by the CPU_CYCLES event on which no
    operation was issued because there are no operations available
    to issue to this PE from the frontend"
  STALL_BACKEND
   "counts every cycle counted by the CPU_CYCLES event on which no
    operation was issued because the backend is unable to accept
    any available operations from the frontend"

QEMU never stalls in this sense, so our implementation is trivial:
always return a zero count.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

---
 target/arm/helper.c | 32 ++++++++++++++++++++++++++++++--
 1 file changed, 30 insertions(+), 2 deletions(-)

-- 
2.20.1

Comments

Richard Henderson Feb. 11, 2020, 6:45 p.m. UTC | #1 
On 2/11/20 9:37 AM, Peter Maydell wrote:
> The ARMv8.1-PMU extension requires:

>  * the evtCount field in PMETYPER<n>_EL0 is 16 bits, not 10

>  * MDCR_EL2.HPMD allows event counting to be disabled at EL2

>  * two new required events, STALL_FRONTEND and STALL_BACKEND

>  * ID register bits in ID_AA64DFR0_EL1 and ID_DFR0

> 

> We already implement the 16-bit evtCount field and the

> HPMD bit, so all that is missing is the two new events:

>   STALL_FRONTEND

>    "counts every cycle counted by the CPU_CYCLES event on which no

>     operation was issued because there are no operations available

>     to issue to this PE from the frontend"

>   STALL_BACKEND

>    "counts every cycle counted by the CPU_CYCLES event on which no

>     operation was issued because the backend is unable to accept

>     any available operations from the frontend"

> 

> QEMU never stalls in this sense, so our implementation is trivial:

> always return a zero count.

> 

> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

> ---

>  target/arm/helper.c | 32 ++++++++++++++++++++++++++++++--

>  1 file changed, 30 insertions(+), 2 deletions(-)


Reviewed-by: Richard Henderson <richard.henderson@linaro.org>



r~
diff mbox series

Patch

diff --git a/target/arm/helper.c b/target/arm/helper.c
index 9537785104e..c896ad0b7ee 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -1124,6 +1124,24 @@  static int64_t instructions_ns_per(uint64_t icount)
 }
 #endif
 
+static bool pmu_8_1_events_supported(CPUARMState *env)
+{
+    /* For events which are supported in any v8.1 PMU */
+    return cpu_isar_feature(any_pmu_8_1, env_archcpu(env));
+}
+
+static uint64_t zero_event_get_count(CPUARMState *env)
+{
+    /* For events which on QEMU never fire, so their count is always zero */
+    return 0;
+}
+
+static int64_t zero_event_ns_per(uint64_t cycles)
+{
+    /* An event which never fires can never overflow */
+    return -1;
+}
+
 static const pm_event pm_events[] = {
     { .number = 0x000, /* SW_INCR */
       .supported = event_always_supported,
@@ -1140,8 +1158,18 @@  static const pm_event pm_events[] = {
       .supported = event_always_supported,
       .get_count = cycles_get_count,
       .ns_per_count = cycles_ns_per,
-    }
+    },
 #endif
+    { .number = 0x023, /* STALL_FRONTEND */
+      .supported = pmu_8_1_events_supported,
+      .get_count = zero_event_get_count,
+      .ns_per_count = zero_event_ns_per,
+    },
+    { .number = 0x024, /* STALL_BACKEND */
+      .supported = pmu_8_1_events_supported,
+      .get_count = zero_event_get_count,
+      .ns_per_count = zero_event_ns_per,
+    },
 };
 
 /*
@@ -1150,7 +1178,7 @@  static const pm_event pm_events[] = {
  * should first be updated to something sparse instead of the current
  * supported_event_map[] array.
  */
-#define MAX_EVENT_ID 0x11
+#define MAX_EVENT_ID 0x24
 #define UNSUPPORTED_EVENT UINT16_MAX
 static uint16_t supported_event_map[MAX_EVENT_ID + 1];