diff mbox series

[06/15] target/arm: Enforce M-profile VMRS/VMSR register restrictions

Message ID 20201116160831.31000-7-peter.maydell@linaro.org
State Superseded
Headers show
Series target/arm: More v8.1M features | expand

Commit Message

Peter Maydell Nov. 16, 2020, 4:08 p.m. UTC 
For M-profile before v8.1M, the only valid register for VMSR/VMRS is
the FPSCR.  We have a comment that states this, but the actual logic
to forbid accesses for any other register value is missing, so we
would end up with A-profile style behaviour.  Add the missing check.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

---
 target/arm/translate-vfp.c.inc | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

-- 
2.20.1

Comments

Richard Henderson Nov. 17, 2020, 7:42 p.m. UTC | #1 
On 11/16/20 8:08 AM, Peter Maydell wrote:
> -        if (a->rt == 15 && (!a->l || a->reg != ARM_VFP_FPSCR)) {

> +        if (a->reg != ARM_VFP_FPSCR) {

> +            return false;

> +        }

> +        if (a->rt == 15 && !a->l) {


Alternately, the parenthesis are just off:

  if ((a->rt == 15 && !a->l) || a->reg != ARM_VFP_FPSCR)

Either way,
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


r~
Peter Maydell Nov. 17, 2020, 9:18 p.m. UTC | #2 
On Tue, 17 Nov 2020 at 19:42, Richard Henderson
<richard.henderson@linaro.org> wrote:
>

> On 11/16/20 8:08 AM, Peter Maydell wrote:

> > -        if (a->rt == 15 && (!a->l || a->reg != ARM_VFP_FPSCR)) {

> > +        if (a->reg != ARM_VFP_FPSCR) {

> > +            return false;

> > +        }

> > +        if (a->rt == 15 && !a->l) {

>

> Alternately, the parenthesis are just off:

>

>   if ((a->rt == 15 && !a->l) || a->reg != ARM_VFP_FPSCR)


Mmm. As you've probably discovered by now, the refactoring
in the subsequent patches means that this code gets moved
and changed anyway; I just wanted it in this separate
patch so the bugfix wasn't hidden in the refactoring.

thanks
-- PMM
diff mbox series

Patch

diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c.inc
index daf39306d04..aee60ff98b3 100644
--- a/target/arm/translate-vfp.c.inc
+++ b/target/arm/translate-vfp.c.inc
@@ -622,7 +622,10 @@  static bool trans_VMSR_VMRS(DisasContext *s, arg_VMSR_VMRS *a)
          * Accesses to R15 are UNPREDICTABLE; we choose to undef.
          * (FPSCR -> r15 is a special case which writes to the PSR flags.)
          */
-        if (a->rt == 15 && (!a->l || a->reg != ARM_VFP_FPSCR)) {
+        if (a->reg != ARM_VFP_FPSCR) {
+            return false;
+        }
+        if (a->rt == 15 && !a->l) {
             return false;
         }
     }