| Message ID | 20220417174426.711829-19-richard.henderson@linaro.org |
|---|---|
| State | Superseded |
| Headers | show |
| Series | target/arm: Cleanups, new features, new cpus | expand |
On Sun, 17 Apr 2022 at 19:02, Richard Henderson <richard.henderson@linaro.org> wrote: > > Use tcg_constant_{i32,i64} as appropriate throughout. > > Signed-off-by: Richard Henderson <richard.henderson@linaro.org> > --- > target/arm/translate-m-nocp.c | 12 +++++------- > 1 file changed, 5 insertions(+), 7 deletions(-) > > diff --git a/target/arm/translate-m-nocp.c b/target/arm/translate-m-nocp.c > index d9e144e8eb..27363a7b4e 100644 > --- a/target/arm/translate-m-nocp.c > +++ b/target/arm/translate-m-nocp.c > @@ -173,7 +173,7 @@ static bool trans_VSCCLRM(DisasContext *s, arg_VSCCLRM *a) > } > > /* Zero the Sregs from btmreg to topreg inclusive. */ > - zero = tcg_const_i64(0); > + zero = tcg_constant_i64(0); > if (btmreg & 1) { > write_neon_element64(zero, btmreg >> 1, 1, MO_32); > btmreg++; Looks like we were previously leaking the TCGv for this one? Reviewed-by: Peter Maydell <peter.maydell@linaro.org> thanks -- PMM
On 4/21/22 12:03, Peter Maydell wrote: > On Sun, 17 Apr 2022 at 19:02, Richard Henderson > <richard.henderson@linaro.org> wrote: >> >> Use tcg_constant_{i32,i64} as appropriate throughout. >> >> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> >> --- >> target/arm/translate-m-nocp.c | 12 +++++------- >> 1 file changed, 5 insertions(+), 7 deletions(-) >> >> diff --git a/target/arm/translate-m-nocp.c b/target/arm/translate-m-nocp.c >> index d9e144e8eb..27363a7b4e 100644 >> --- a/target/arm/translate-m-nocp.c >> +++ b/target/arm/translate-m-nocp.c >> @@ -173,7 +173,7 @@ static bool trans_VSCCLRM(DisasContext *s, arg_VSCCLRM *a) >> } >> >> /* Zero the Sregs from btmreg to topreg inclusive. */ >> - zero = tcg_const_i64(0); >> + zero = tcg_constant_i64(0); >> if (btmreg & 1) { >> write_neon_element64(zero, btmreg >> 1, 1, MO_32); >> btmreg++; > > Looks like we were previously leaking the TCGv for this one? Yes. I'll update the commit message to mention that. r~
diff --git a/target/arm/translate-m-nocp.c b/target/arm/translate-m-nocp.c index d9e144e8eb..27363a7b4e 100644 --- a/target/arm/translate-m-nocp.c +++ b/target/arm/translate-m-nocp.c @@ -173,7 +173,7 @@ static bool trans_VSCCLRM(DisasContext *s, arg_VSCCLRM *a) } /* Zero the Sregs from btmreg to topreg inclusive. */ - zero = tcg_const_i64(0); + zero = tcg_constant_i64(0); if (btmreg & 1) { write_neon_element64(zero, btmreg >> 1, 1, MO_32); btmreg++; @@ -187,8 +187,7 @@ static bool trans_VSCCLRM(DisasContext *s, arg_VSCCLRM *a) } assert(btmreg == topreg + 1); if (dc_isar_feature(aa32_mve, s)) { - TCGv_i32 z32 = tcg_const_i32(0); - store_cpu_field(z32, v7m.vpr); + store_cpu_field(tcg_constant_i32(0), v7m.vpr); } clear_eci_state(s); @@ -512,7 +511,7 @@ static bool gen_M_fp_sysreg_read(DisasContext *s, int regno, } case ARM_VFP_FPCXT_NS: { - TCGv_i32 control, sfpa, fpscr, fpdscr, zero; + TCGv_i32 control, sfpa, fpscr, fpdscr; TCGLabel *lab_active = gen_new_label(); lookup_tb = true; @@ -552,10 +551,9 @@ static bool gen_M_fp_sysreg_read(DisasContext *s, int regno, storefn(s, opaque, tmp, true); /* If SFPA is zero then set FPSCR from FPDSCR_NS */ fpdscr = load_cpu_field(v7m.fpdscr[M_REG_NS]); - zero = tcg_const_i32(0); - tcg_gen_movcond_i32(TCG_COND_EQ, fpscr, sfpa, zero, fpdscr, fpscr); + tcg_gen_movcond_i32(TCG_COND_EQ, fpscr, sfpa, tcg_constant_i32(0), + fpdscr, fpscr); gen_helper_vfp_set_fpscr(cpu_env, fpscr); - tcg_temp_free_i32(zero); tcg_temp_free_i32(sfpa); tcg_temp_free_i32(fpdscr); tcg_temp_free_i32(fpscr);
Use tcg_constant_{i32,i64} as appropriate throughout. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- target/arm/translate-m-nocp.c | 12 +++++------- 1 file changed, 5 insertions(+), 7 deletions(-)