| Message ID | 20220503194843.1379101-17-richard.henderson@linaro.org |
|---|---|
| State | Superseded |
| Headers | show |
| Series | semihosting cleanup | expand |
On Wed, May 4, 2022 at 6:11 AM Richard Henderson <richard.henderson@linaro.org> wrote: > > We already have some larger ifdef blocks for ARM and RISCV; > split the function into multiple implementations per arch. > > Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > semihosting/arm-compat-semi.c | 19 ++++++++----------- > 1 file changed, 8 insertions(+), 11 deletions(-) > > diff --git a/semihosting/arm-compat-semi.c b/semihosting/arm-compat-semi.c > index a6c6e5baf6..7fc60e223a 100644 > --- a/semihosting/arm-compat-semi.c > +++ b/semihosting/arm-compat-semi.c > @@ -213,6 +213,10 @@ common_semi_sys_exit_extended(CPUState *cs, int nr) > return (nr == TARGET_SYS_EXIT_EXTENDED || is_a64(cs->env_ptr)); > } > > +static inline bool is_64bit_semihosting(CPUArchState *env) > +{ > + return is_a64(env); > +} > #endif /* TARGET_ARM */ > > #ifdef TARGET_RISCV > @@ -238,6 +242,10 @@ common_semi_sys_exit_extended(CPUState *cs, int nr) > return (nr == TARGET_SYS_EXIT_EXTENDED || sizeof(target_ulong) == 8); > } > > +static inline bool is_64bit_semihosting(CPUArchState *env) > +{ > + return riscv_cpu_mxl(env) != MXL_RV32; > +} > #endif > > /* > @@ -586,17 +594,6 @@ static const GuestFDFunctions guestfd_fns[] = { > * call if the memory read fails. Eventually we could use a generic > * CPUState helper function here. > */ > -static inline bool is_64bit_semihosting(CPUArchState *env) > -{ > -#if defined(TARGET_ARM) > - return is_a64(env); > -#elif defined(TARGET_RISCV) > - return riscv_cpu_mxl(env) != MXL_RV32; > -#else > -#error un-handled architecture > -#endif > -} > - > > #define GET_ARG(n) do { \ > if (is_64bit_semihosting(env)) { \ > -- > 2.34.1 > >
diff --git a/semihosting/arm-compat-semi.c b/semihosting/arm-compat-semi.c index a6c6e5baf6..7fc60e223a 100644 --- a/semihosting/arm-compat-semi.c +++ b/semihosting/arm-compat-semi.c @@ -213,6 +213,10 @@ common_semi_sys_exit_extended(CPUState *cs, int nr) return (nr == TARGET_SYS_EXIT_EXTENDED || is_a64(cs->env_ptr)); } +static inline bool is_64bit_semihosting(CPUArchState *env) +{ + return is_a64(env); +} #endif /* TARGET_ARM */ #ifdef TARGET_RISCV @@ -238,6 +242,10 @@ common_semi_sys_exit_extended(CPUState *cs, int nr) return (nr == TARGET_SYS_EXIT_EXTENDED || sizeof(target_ulong) == 8); } +static inline bool is_64bit_semihosting(CPUArchState *env) +{ + return riscv_cpu_mxl(env) != MXL_RV32; +} #endif /* @@ -586,17 +594,6 @@ static const GuestFDFunctions guestfd_fns[] = { * call if the memory read fails. Eventually we could use a generic * CPUState helper function here. */ -static inline bool is_64bit_semihosting(CPUArchState *env) -{ -#if defined(TARGET_ARM) - return is_a64(env); -#elif defined(TARGET_RISCV) - return riscv_cpu_mxl(env) != MXL_RV32; -#else -#error un-handled architecture -#endif -} - #define GET_ARG(n) do { \ if (is_64bit_semihosting(env)) { \
We already have some larger ifdef blocks for ARM and RISCV; split the function into multiple implementations per arch. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- semihosting/arm-compat-semi.c | 19 ++++++++----------- 1 file changed, 8 insertions(+), 11 deletions(-)