| Message ID | 20220503194843.1379101-18-richard.henderson@linaro.org |
|---|---|
| State | Superseded |
| Headers | show |
| Series | semihosting cleanup | expand |
On Wed, May 4, 2022 at 5:59 AM Richard Henderson <richard.henderson@linaro.org> wrote: > > We already have some larger ifdef blocks for ARM and RISCV; > split out common_semi_stack_bottom per target. > > Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > semihosting/arm-compat-semi.c | 44 +++++++++++++++++------------------ > 1 file changed, 21 insertions(+), 23 deletions(-) > > diff --git a/semihosting/arm-compat-semi.c b/semihosting/arm-compat-semi.c > index 7fc60e223a..b2816e9f66 100644 > --- a/semihosting/arm-compat-semi.c > +++ b/semihosting/arm-compat-semi.c > @@ -217,6 +217,13 @@ static inline bool is_64bit_semihosting(CPUArchState *env) > { > return is_a64(env); > } > + > +static inline target_ulong common_semi_stack_bottom(CPUState *cs) > +{ > + ARMCPU *cpu = ARM_CPU(cs); > + CPUARMState *env = &cpu->env; > + return is_a64(env) ? env->xregs[31] : env->regs[13]; > +} > #endif /* TARGET_ARM */ > > #ifdef TARGET_RISCV > @@ -246,6 +253,13 @@ static inline bool is_64bit_semihosting(CPUArchState *env) > { > return riscv_cpu_mxl(env) != MXL_RV32; > } > + > +static inline target_ulong common_semi_stack_bottom(CPUState *cs) > +{ > + RISCVCPU *cpu = RISCV_CPU(cs); > + CPURISCVState *env = &cpu->env; > + return env->gpr[xSP]; > +} > #endif > > /* > @@ -301,31 +315,15 @@ static void common_semi_cb(CPUState *cs, target_ulong ret, target_ulong err) > common_semi_set_ret(cs, ret); > } > > +/* > + * Return an address in target memory of 64 bytes where the remote > + * gdb should write its stat struct. (The format of this structure > + * is defined by GDB's remote protocol and is not target-specific.) > + * We put this on the guest's stack just below SP. > + */ > static target_ulong common_semi_flen_buf(CPUState *cs) > { > - target_ulong sp; > -#ifdef TARGET_ARM > - /* Return an address in target memory of 64 bytes where the remote > - * gdb should write its stat struct. (The format of this structure > - * is defined by GDB's remote protocol and is not target-specific.) > - * We put this on the guest's stack just below SP. > - */ > - ARMCPU *cpu = ARM_CPU(cs); > - CPUARMState *env = &cpu->env; > - > - if (is_a64(env)) { > - sp = env->xregs[31]; > - } else { > - sp = env->regs[13]; > - } > -#endif > -#ifdef TARGET_RISCV > - RISCVCPU *cpu = RISCV_CPU(cs); > - CPURISCVState *env = &cpu->env; > - > - sp = env->gpr[xSP]; > -#endif > - > + target_ulong sp = common_semi_stack_bottom(cs); > return sp - 64; > } > > -- > 2.34.1 > >
diff --git a/semihosting/arm-compat-semi.c b/semihosting/arm-compat-semi.c index 7fc60e223a..b2816e9f66 100644 --- a/semihosting/arm-compat-semi.c +++ b/semihosting/arm-compat-semi.c @@ -217,6 +217,13 @@ static inline bool is_64bit_semihosting(CPUArchState *env) { return is_a64(env); } + +static inline target_ulong common_semi_stack_bottom(CPUState *cs) +{ + ARMCPU *cpu = ARM_CPU(cs); + CPUARMState *env = &cpu->env; + return is_a64(env) ? env->xregs[31] : env->regs[13]; +} #endif /* TARGET_ARM */ #ifdef TARGET_RISCV @@ -246,6 +253,13 @@ static inline bool is_64bit_semihosting(CPUArchState *env) { return riscv_cpu_mxl(env) != MXL_RV32; } + +static inline target_ulong common_semi_stack_bottom(CPUState *cs) +{ + RISCVCPU *cpu = RISCV_CPU(cs); + CPURISCVState *env = &cpu->env; + return env->gpr[xSP]; +} #endif /* @@ -301,31 +315,15 @@ static void common_semi_cb(CPUState *cs, target_ulong ret, target_ulong err) common_semi_set_ret(cs, ret); } +/* + * Return an address in target memory of 64 bytes where the remote + * gdb should write its stat struct. (The format of this structure + * is defined by GDB's remote protocol and is not target-specific.) + * We put this on the guest's stack just below SP. + */ static target_ulong common_semi_flen_buf(CPUState *cs) { - target_ulong sp; -#ifdef TARGET_ARM - /* Return an address in target memory of 64 bytes where the remote - * gdb should write its stat struct. (The format of this structure - * is defined by GDB's remote protocol and is not target-specific.) - * We put this on the guest's stack just below SP. - */ - ARMCPU *cpu = ARM_CPU(cs); - CPUARMState *env = &cpu->env; - - if (is_a64(env)) { - sp = env->xregs[31]; - } else { - sp = env->regs[13]; - } -#endif -#ifdef TARGET_RISCV - RISCVCPU *cpu = RISCV_CPU(cs); - CPURISCVState *env = &cpu->env; - - sp = env->gpr[xSP]; -#endif - + target_ulong sp = common_semi_stack_bottom(cs); return sp - 64; }
We already have some larger ifdef blocks for ARM and RISCV; split out common_semi_stack_bottom per target. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- semihosting/arm-compat-semi.c | 44 +++++++++++++++++------------------ 1 file changed, 21 insertions(+), 23 deletions(-)