@@ -71,8 +71,7 @@ static uint64_t mpc8544_guts_read(void *opaque, hwaddr addr,
unsigned size)
{
uint32_t value = 0;
- PowerPCCPU *cpu = POWERPC_CPU(current_cpu);
- CPUPPCState *env = &cpu->env;
+ CPUPPCState *env = cpu_env(current_cpu);
addr &= MPC8544_GUTS_MMIO_SIZE - 1;
switch (addr) {
@@ -2294,8 +2294,7 @@ static void pnv_machine_set_hb(Object *obj, bool value, Error **errp)
static void pnv_cpu_do_nmi_on_cpu(CPUState *cs, run_on_cpu_data arg)
{
- PowerPCCPU *cpu = POWERPC_CPU(cs);
- CPUPPCState *env = &cpu->env;
+ CPUPPCState *env = cpu_env(cs);
cpu_synchronize_state(cs);
ppc_cpu_do_system_reset(cs);
@@ -44,15 +44,12 @@ static void xscom_complete(CPUState *cs, uint64_t hmer_bits)
* passed for the cpu, and no CPU completion is generated.
*/
if (cs) {
- PowerPCCPU *cpu = POWERPC_CPU(cs);
- CPUPPCState *env = &cpu->env;
-
/*
* TODO: Need a CPU helper to set HMER, also handle generation
* of HMIs
*/
cpu_synchronize_state(cs);
- env->spr[SPR_HMER] |= hmer_bits;
+ cpu_env(cs)->spr[SPR_HMER] |= hmer_bits;
}
}
@@ -90,8 +90,7 @@ static void mmubooke_create_initial_mapping(CPUPPCState *env,
static void spin_kick(CPUState *cs, run_on_cpu_data data)
{
- PowerPCCPU *cpu = POWERPC_CPU(cs);
- CPUPPCState *env = &cpu->env;
+ CPUPPCState *env = cpu_env(cs);
SpinInfo *curspin = data.host_ptr;
hwaddr map_size = 64 * MiB;
hwaddr map_start;
@@ -3487,8 +3487,7 @@ static void spapr_machine_finalizefn(Object *obj)
void spapr_do_system_reset_on_cpu(CPUState *cs, run_on_cpu_data arg)
{
SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine());
- PowerPCCPU *cpu = POWERPC_CPU(cs);
- CPUPPCState *env = &cpu->env;
+ CPUPPCState *env = cpu_env(cs);
cpu_synchronize_state(cs);
/* If FWNMI is inactive, addr will be -1, which will deliver to 0x100 */
@@ -194,8 +194,7 @@ static void cap_htm_apply(SpaprMachineState *spapr, uint8_t val, Error **errp)
static void cap_vsx_apply(SpaprMachineState *spapr, uint8_t val, Error **errp)
{
ERRP_GUARD();
- PowerPCCPU *cpu = POWERPC_CPU(first_cpu);
- CPUPPCState *env = &cpu->env;
+ CPUPPCState *env = cpu_env(first_cpu);
if (!val) {
/* TODO: We don't support disabling vsx yet */
@@ -213,8 +212,7 @@ static void cap_vsx_apply(SpaprMachineState *spapr, uint8_t val, Error **errp)
static void cap_dfp_apply(SpaprMachineState *spapr, uint8_t val, Error **errp)
{
ERRP_GUARD();
- PowerPCCPU *cpu = POWERPC_CPU(first_cpu);
- CPUPPCState *env = &cpu->env;
+ CPUPPCState *env = cpu_env(first_cpu);
if (!val) {
/* TODO: We don't support disabling dfp yet */
@@ -7195,12 +7195,9 @@ static void ppc_cpu_reset_hold(Object *obj)
static bool ppc_cpu_is_big_endian(CPUState *cs)
{
- PowerPCCPU *cpu = POWERPC_CPU(cs);
- CPUPPCState *env = &cpu->env;
-
cpu_synchronize_state(cs);
- return !FIELD_EX64(env->msr, MSR, LE);
+ return !FIELD_EX64(cpu_env(cs)->msr, MSR, LE);
}
static bool ppc_get_irq_stats(InterruptStatsProvider *obj,
@@ -7287,8 +7284,7 @@ static bool ppc_pvr_match_default(PowerPCCPUClass *pcc, uint32_t pvr, bool best)
static void ppc_disas_set_info(CPUState *cs, disassemble_info *info)
{
- PowerPCCPU *cpu = POWERPC_CPU(cs);
- CPUPPCState *env = &cpu->env;
+ CPUPPCState *env = cpu_env(cs);
if ((env->hflags >> MSR_LE) & 1) {
info->endian = BFD_ENDIAN_LITTLE;
@@ -7446,8 +7442,7 @@ void ppc_cpu_dump_state(CPUState *cs, FILE *f, int flags)
#define RGPL 4
#define RFPL 4
- PowerPCCPU *cpu = POWERPC_CPU(cs);
- CPUPPCState *env = &cpu->env;
+ CPUPPCState *env = cpu_env(cs);
int i;
qemu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR "
@@ -2588,8 +2588,7 @@ void ppc_cpu_do_fwnmi_machine_check(CPUState *cs, target_ulong vector)
bool ppc_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
{
- PowerPCCPU *cpu = POWERPC_CPU(cs);
- CPUPPCState *env = &cpu->env;
+ CPUPPCState *env = cpu_env(cs);
int interrupt;
if ((interrupt_request & CPU_INTERRUPT_HARD) == 0) {
@@ -108,8 +108,7 @@ void ppc_maybe_bswap_register(CPUPPCState *env, uint8_t *mem_buf, int len)
int ppc_cpu_gdb_read_register(CPUState *cs, GByteArray *buf, int n)
{
- PowerPCCPU *cpu = POWERPC_CPU(cs);
- CPUPPCState *env = &cpu->env;
+ CPUPPCState *env = cpu_env(cs);
uint8_t *mem_buf;
int r = ppc_gdb_register_len(n);
@@ -152,8 +151,7 @@ int ppc_cpu_gdb_read_register(CPUState *cs, GByteArray *buf, int n)
int ppc_cpu_gdb_read_register_apple(CPUState *cs, GByteArray *buf, int n)
{
- PowerPCCPU *cpu = POWERPC_CPU(cs);
- CPUPPCState *env = &cpu->env;
+ CPUPPCState *env = cpu_env(cs);
uint8_t *mem_buf;
int r = ppc_gdb_register_len_apple(n);
@@ -206,8 +204,7 @@ int ppc_cpu_gdb_read_register_apple(CPUState *cs, GByteArray *buf, int n)
int ppc_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
{
- PowerPCCPU *cpu = POWERPC_CPU(cs);
- CPUPPCState *env = &cpu->env;
+ CPUPPCState *env = cpu_env(cs);
int r = ppc_gdb_register_len(n);
if (!r) {
@@ -253,8 +250,7 @@ int ppc_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
}
int ppc_cpu_gdb_write_register_apple(CPUState *cs, uint8_t *mem_buf, int n)
{
- PowerPCCPU *cpu = POWERPC_CPU(cs);
- CPUPPCState *env = &cpu->env;
+ CPUPPCState *env = cpu_env(cs);
int r = ppc_gdb_register_len_apple(n);
if (!r) {
@@ -546,8 +546,7 @@ static void kvm_sw_tlb_put(PowerPCCPU *cpu)
static void kvm_get_one_spr(CPUState *cs, uint64_t id, int spr)
{
- PowerPCCPU *cpu = POWERPC_CPU(cs);
- CPUPPCState *env = &cpu->env;
+ CPUPPCState *env = cpu_env(cs);
/* Init 'val' to avoid "uninitialised value" Valgrind warnings */
union {
uint32_t u32;
@@ -581,8 +580,7 @@ static void kvm_get_one_spr(CPUState *cs, uint64_t id, int spr)
static void kvm_put_one_spr(CPUState *cs, uint64_t id, int spr)
{
- PowerPCCPU *cpu = POWERPC_CPU(cs);
- CPUPPCState *env = &cpu->env;
+ CPUPPCState *env = cpu_env(cs);
union {
uint32_t u32;
uint64_t u64;
@@ -133,8 +133,7 @@ static int ppc_cpu_get_reg_num(const char *numstr, int maxnum, int *pregnum)
int target_get_monitor_def(CPUState *cs, const char *name, uint64_t *pval)
{
int i, regnum;
- PowerPCCPU *cpu = POWERPC_CPU(cs);
- CPUPPCState *env = &cpu->env;
+ CPUPPCState *env = cpu_env(cs);
/* General purpose registers */
if ((qemu_tolower(name[0]) == 'r') &&
@@ -27,8 +27,7 @@ void ppc_cpu_record_sigsegv(CPUState *cs, vaddr address,
MMUAccessType access_type,
bool maperr, uintptr_t retaddr)
{
- PowerPCCPU *cpu = POWERPC_CPU(cs);
- CPUPPCState *env = &cpu->env;
+ CPUPPCState *env = cpu_env(cs);
int exception, error_code;
/*
Mechanical patch produced running the command documented in scripts/coccinelle/cpu_env.cocci_template header. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> --- hw/ppc/mpc8544_guts.c | 3 +-- hw/ppc/pnv.c | 3 +-- hw/ppc/pnv_xscom.c | 5 +---- hw/ppc/ppce500_spin.c | 3 +-- hw/ppc/spapr.c | 3 +-- hw/ppc/spapr_caps.c | 6 ++---- target/ppc/cpu_init.c | 11 +++-------- target/ppc/excp_helper.c | 3 +-- target/ppc/gdbstub.c | 12 ++++-------- target/ppc/kvm.c | 6 ++---- target/ppc/ppc-qmp-cmds.c | 3 +-- target/ppc/user_only_helper.c | 3 +-- 12 files changed, 19 insertions(+), 42 deletions(-)