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[v3,01/23] i2c: designware_i2c: Add more registers

Message ID 20200123114556.v3.1.If37e17d4b2c18747bafd9953e17d5014626a9f71@changeid
State Accepted
Commit 0fd05c9dcfd1f355bcc426cd263da8b2b85706ad
Headers show
Series i2c: designware_ic2: Improvements to timing and general cleanup | expand

Commit Message

Simon Glass Jan. 23, 2020, 6:48 p.m. UTC 
Some versions of this peripherals provide more control of the bus
behaviour. Add definitions for these registers.

Signed-off-by: Simon Glass <sjg at chromium.org>
Reviewed-by: Ley Foon Tan <ley.foon.tan at intel.com>
Reviewed-by: Jun Chen <ptchentw at gmail.com>
Reviewed-by: Heiko Schocher <hs at denx.de>
---

Changes in v3:
- Fix the address of comp_param1 by adding a gap

Changes in v2:
- Fix 'previde' typo

 drivers/i2c/designware_i2c.h | 14 +++++++++++++-
 1 file changed, 13 insertions(+), 1 deletion(-)
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Patch

diff --git a/drivers/i2c/designware_i2c.h b/drivers/i2c/designware_i2c.h
index 48766d0806..3b407d2bed 100644
--- a/drivers/i2c/designware_i2c.h
+++ b/drivers/i2c/designware_i2c.h
@@ -43,8 +43,20 @@  struct i2c_regs {
 	u32 ic_rxflr;		/* 0x78 */
 	u32 ic_sda_hold;	/* 0x7c */
 	u32 ic_tx_abrt_source;	/* 0x80 */
-	u8 res1[0x18];		/* 0x84 */
+	u32 slv_data_nak_only;
+	u32 dma_cr;
+	u32 dma_tdlr;
+	u32 dma_rdlr;
+	u32 sda_setup;
+	u32 ack_general_call;
 	u32 ic_enable_status;	/* 0x9c */
+	u32 fs_spklen;
+	u32 hs_spklen;
+	u32 clr_restart_det;
+	u8 reserved[0xf4 - 0xac];
+	u32 comp_param1;	/* 0xf4 */
+	u32 comp_version;
+	u32 comp_type;
 };
 
 #if !defined(IC_CLK)