diff mbox series

[v2,09/12] hw/arm/virt: spe: Add SPE fdt binding for virt machine

Message ID c6ac607d2cd253de6a990538edfde7f86066f04f.1599549462.git.haibo.xu@linaro.org
State New
Headers show
Series target/arm: Add vSPE support to KVM guest | expand

Commit Message

Haibo Xu Sept. 8, 2020, 8:13 a.m. UTC 
Add a virtual SPE device for virt machine while using
PPI 5 for SPE overflow interrupt number which has already
selected in kvmtool.

Signed-off-by: Haibo Xu <haibo.xu@linaro.org>

---
 hw/arm/virt-acpi-build.c    |  3 +++
 hw/arm/virt.c               | 43 ++++++++++++++++++++++++++++++++++++-
 include/hw/acpi/acpi-defs.h |  3 +++
 include/hw/arm/virt.h       |  1 +
 target/arm/cpu.c            |  2 ++
 target/arm/cpu.h            |  2 ++
 6 files changed, 53 insertions(+), 1 deletion(-)

-- 
2.17.1

Comments

Andrew Jones Sept. 8, 2020, 11:16 a.m. UTC | #1 
This patch does much more than the summary "hw/arm/virt: spe: Add SPE fdt
binding for virt machine" says it does. Please revise the summary.

On Tue, Sep 08, 2020 at 08:13:27AM +0000, Haibo Xu wrote:
> Add a virtual SPE device for virt machine while using

> PPI 5 for SPE overflow interrupt number which has already

> selected in kvmtool.

> 

> Signed-off-by: Haibo Xu <haibo.xu@linaro.org>

> ---

>  hw/arm/virt-acpi-build.c    |  3 +++

>  hw/arm/virt.c               | 43 ++++++++++++++++++++++++++++++++++++-

>  include/hw/acpi/acpi-defs.h |  3 +++

>  include/hw/arm/virt.h       |  1 +

>  target/arm/cpu.c            |  2 ++

>  target/arm/cpu.h            |  2 ++

>  6 files changed, 53 insertions(+), 1 deletion(-)

> 

> diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c

> index 9efd7a3881..3fd80fda53 100644

> --- a/hw/arm/virt-acpi-build.c

> +++ b/hw/arm/virt-acpi-build.c

> @@ -665,6 +665,9 @@ build_madt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)

>          if (arm_feature(&armcpu->env, ARM_FEATURE_PMU)) {

>              gicc->performance_interrupt = cpu_to_le32(PPI(VIRTUAL_PMU_IRQ));

>          }

> +        if (cpu_isar_feature(aa64_spe, armcpu)) {

> +            gicc->spe_interrupt = cpu_to_le32(PPI(VIRTUAL_SPE_IRQ));

> +        }

>          if (vms->virt) {

>              gicc->vgic_interrupt = cpu_to_le32(PPI(ARCH_GIC_MAINT_IRQ));

>          }

> diff --git a/hw/arm/virt.c b/hw/arm/virt.c

> index 6bacfb668d..bdb1ce925c 100644

> --- a/hw/arm/virt.c

> +++ b/hw/arm/virt.c

> @@ -545,6 +545,32 @@ static void fdt_add_pmu_nodes(const VirtMachineState *vms)

>      }

>  }

>  

> +static void fdt_add_spe_nodes(const VirtMachineState *vms)

> +{

> +    ARMCPU *armcpu = ARM_CPU(first_cpu);

> +    uint32_t irqflags = GIC_FDT_IRQ_FLAGS_LEVEL_HI;

> +

> +    if (!cpu_isar_feature(aa64_spe, armcpu)) {

> +        assert(!object_property_get_bool(OBJECT(armcpu), "spe", NULL));

> +        return;

> +    }

> +

> +    if (vms->gic_version == VIRT_GIC_VERSION_2) {

> +        irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START,

> +                             GIC_FDT_IRQ_PPI_CPU_WIDTH,

> +                             (1 << vms->smp_cpus) - 1);

> +    }

> +

> +    qemu_fdt_add_subnode(vms->fdt, "/spe");

> +    if (arm_feature(&armcpu->env, ARM_FEATURE_V8)) {

> +        const char compat[] = "arm,statistical-profiling-extension-v1";

> +        qemu_fdt_setprop(vms->fdt, "/spe", "compatible",

> +                         compat, sizeof(compat));

> +        qemu_fdt_setprop_cells(vms->fdt, "/spe", "interrupts",

> +                               GIC_FDT_IRQ_TYPE_PPI, VIRTUAL_SPE_IRQ, irqflags);

> +    }

> +}

> +

>  static inline DeviceState *create_acpi_ged(VirtMachineState *vms)

>  {

>      DeviceState *dev;

> @@ -717,6 +743,10 @@ static void create_gic(VirtMachineState *vms)

>                                      qdev_get_gpio_in(vms->gic, ppibase

>                                                       + VIRTUAL_PMU_IRQ));

>  

> +        qdev_connect_gpio_out_named(cpudev, "spe-interrupt", 0,

> +                                    qdev_get_gpio_in(vms->gic, ppibase

> +                                                     + VIRTUAL_SPE_IRQ));

> +

>          sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ));

>          sysbus_connect_irq(gicbusdev, i + smp_cpus,

>                             qdev_get_gpio_in(cpudev, ARM_CPU_FIQ));

> @@ -1664,11 +1694,12 @@ static void finalize_gic_version(VirtMachineState *vms)

>  

>  static void virt_cpu_post_init(VirtMachineState *vms)

>  {

> -    bool aarch64, pmu;

> +    bool aarch64, pmu, spe;

>      CPUState *cpu;

>  

>      aarch64 = object_property_get_bool(OBJECT(first_cpu), "aarch64", NULL);

>      pmu = object_property_get_bool(OBJECT(first_cpu), "pmu", NULL);

> +    spe = object_property_get_bool(OBJECT(first_cpu), "spe", NULL);

>  

>      if (kvm_enabled()) {

>          CPU_FOREACH(cpu) {

> @@ -1679,6 +1710,14 @@ static void virt_cpu_post_init(VirtMachineState *vms)

>                  }

>                  kvm_arm_pmu_init(cpu);

>              }

> +

> +            if (spe) {

> +                assert(ARM_CPU(cpu)->has_spe == ON_OFF_AUTO_ON);

> +                if (kvm_irqchip_in_kernel()) {

> +                    kvm_arm_spe_set_irq(cpu, PPI(VIRTUAL_SPE_IRQ));

> +                }

> +                kvm_arm_spe_init(cpu);


A later patch introduces userspace irqchip support. Should we avoid
allowing it until then to avoid breaking bisection?

> +            }

>          }

>      } else {

>          if (aarch64 && vms->highmem) {

> @@ -1927,6 +1966,8 @@ static void machvirt_init(MachineState *machine)

>  

>      fdt_add_pmu_nodes(vms);

>  

> +    fdt_add_spe_nodes(vms);

> +

>      create_uart(vms, VIRT_UART, sysmem, serial_hd(0));

>  

>      if (vms->secure) {

> diff --git a/include/hw/acpi/acpi-defs.h b/include/hw/acpi/acpi-defs.h

> index 38a42f409a..21e58f27c5 100644

> --- a/include/hw/acpi/acpi-defs.h

> +++ b/include/hw/acpi/acpi-defs.h

> @@ -302,6 +302,9 @@ struct AcpiMadtGenericCpuInterface {

>      uint32_t vgic_interrupt;

>      uint64_t gicr_base_address;

>      uint64_t arm_mpidr;

> +    uint8_t  efficiency_class;

> +    uint8_t  reserved2[1];

> +    uint16_t spe_interrupt; /* ACPI 6.3 */

>  } QEMU_PACKED;

>  

>  typedef struct AcpiMadtGenericCpuInterface AcpiMadtGenericCpuInterface;

> diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h

> index 72c269aaa5..6013b6d535 100644

> --- a/include/hw/arm/virt.h

> +++ b/include/hw/arm/virt.h

> @@ -49,6 +49,7 @@

>  #define ARCH_TIMER_NS_EL1_IRQ 14

>  #define ARCH_TIMER_NS_EL2_IRQ 10

>  

> +#define VIRTUAL_SPE_IRQ 5

>  #define VIRTUAL_PMU_IRQ 7

>  

>  #define PPI(irq) ((irq) + 16)

> diff --git a/target/arm/cpu.c b/target/arm/cpu.c

> index f211958eaa..786cc6134c 100644

> --- a/target/arm/cpu.c

> +++ b/target/arm/cpu.c

> @@ -1041,6 +1041,8 @@ static void arm_cpu_initfn(Object *obj)

>                               "gicv3-maintenance-interrupt", 1);

>      qdev_init_gpio_out_named(DEVICE(cpu), &cpu->pmu_interrupt,

>                               "pmu-interrupt", 1);

> +    qdev_init_gpio_out_named(DEVICE(cpu), &cpu->spe_interrupt,

> +                             "spe-interrupt", 1);

>  #endif

>  

>      /* DTB consumers generally don't in fact care what the 'compatible'

> diff --git a/target/arm/cpu.h b/target/arm/cpu.h

> index baf2bbcee8..395a1e5df8 100644

> --- a/target/arm/cpu.h

> +++ b/target/arm/cpu.h

> @@ -800,6 +800,8 @@ struct ARMCPU {

>      qemu_irq gicv3_maintenance_interrupt;

>      /* GPIO output for the PMU interrupt */

>      qemu_irq pmu_interrupt;

> +    /* GPIO output for the SPE interrupt */

> +    qemu_irq spe_interrupt;

>  

>      /* MemoryRegion to use for secure physical accesses */

>      MemoryRegion *secure_memory;

> -- 

> 2.17.1

> 

> 


Otherwise

Reviewed-by: Andrew Jones <drjones@redhat.com>
Haibo Xu Sept. 9, 2020, 7:51 a.m. UTC | #2 
On Tue, 8 Sep 2020 at 19:16, Andrew Jones <drjones@redhat.com> wrote:
>

>

> This patch does much more than the summary "hw/arm/virt: spe: Add SPE fdt

> binding for virt machine" says it does. Please revise the summary.

>


Will revise it in v3.

Thanks,
Haibo

> On Tue, Sep 08, 2020 at 08:13:27AM +0000, Haibo Xu wrote:

> > Add a virtual SPE device for virt machine while using

> > PPI 5 for SPE overflow interrupt number which has already

> > selected in kvmtool.

> >

> > Signed-off-by: Haibo Xu <haibo.xu@linaro.org>

> > ---

> >  hw/arm/virt-acpi-build.c    |  3 +++

> >  hw/arm/virt.c               | 43 ++++++++++++++++++++++++++++++++++++-

> >  include/hw/acpi/acpi-defs.h |  3 +++

> >  include/hw/arm/virt.h       |  1 +

> >  target/arm/cpu.c            |  2 ++

> >  target/arm/cpu.h            |  2 ++

> >  6 files changed, 53 insertions(+), 1 deletion(-)

> >

> > diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c

> > index 9efd7a3881..3fd80fda53 100644

> > --- a/hw/arm/virt-acpi-build.c

> > +++ b/hw/arm/virt-acpi-build.c

> > @@ -665,6 +665,9 @@ build_madt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)

> >          if (arm_feature(&armcpu->env, ARM_FEATURE_PMU)) {

> >              gicc->performance_interrupt = cpu_to_le32(PPI(VIRTUAL_PMU_IRQ));

> >          }

> > +        if (cpu_isar_feature(aa64_spe, armcpu)) {

> > +            gicc->spe_interrupt = cpu_to_le32(PPI(VIRTUAL_SPE_IRQ));

> > +        }

> >          if (vms->virt) {

> >              gicc->vgic_interrupt = cpu_to_le32(PPI(ARCH_GIC_MAINT_IRQ));

> >          }

> > diff --git a/hw/arm/virt.c b/hw/arm/virt.c

> > index 6bacfb668d..bdb1ce925c 100644

> > --- a/hw/arm/virt.c

> > +++ b/hw/arm/virt.c

> > @@ -545,6 +545,32 @@ static void fdt_add_pmu_nodes(const VirtMachineState *vms)

> >      }

> >  }

> >

> > +static void fdt_add_spe_nodes(const VirtMachineState *vms)

> > +{

> > +    ARMCPU *armcpu = ARM_CPU(first_cpu);

> > +    uint32_t irqflags = GIC_FDT_IRQ_FLAGS_LEVEL_HI;

> > +

> > +    if (!cpu_isar_feature(aa64_spe, armcpu)) {

> > +        assert(!object_property_get_bool(OBJECT(armcpu), "spe", NULL));

> > +        return;

> > +    }

> > +

> > +    if (vms->gic_version == VIRT_GIC_VERSION_2) {

> > +        irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START,

> > +                             GIC_FDT_IRQ_PPI_CPU_WIDTH,

> > +                             (1 << vms->smp_cpus) - 1);

> > +    }

> > +

> > +    qemu_fdt_add_subnode(vms->fdt, "/spe");

> > +    if (arm_feature(&armcpu->env, ARM_FEATURE_V8)) {

> > +        const char compat[] = "arm,statistical-profiling-extension-v1";

> > +        qemu_fdt_setprop(vms->fdt, "/spe", "compatible",

> > +                         compat, sizeof(compat));

> > +        qemu_fdt_setprop_cells(vms->fdt, "/spe", "interrupts",

> > +                               GIC_FDT_IRQ_TYPE_PPI, VIRTUAL_SPE_IRQ, irqflags);

> > +    }

> > +}

> > +

> >  static inline DeviceState *create_acpi_ged(VirtMachineState *vms)

> >  {

> >      DeviceState *dev;

> > @@ -717,6 +743,10 @@ static void create_gic(VirtMachineState *vms)

> >                                      qdev_get_gpio_in(vms->gic, ppibase

> >                                                       + VIRTUAL_PMU_IRQ));

> >

> > +        qdev_connect_gpio_out_named(cpudev, "spe-interrupt", 0,

> > +                                    qdev_get_gpio_in(vms->gic, ppibase

> > +                                                     + VIRTUAL_SPE_IRQ));

> > +

> >          sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ));

> >          sysbus_connect_irq(gicbusdev, i + smp_cpus,

> >                             qdev_get_gpio_in(cpudev, ARM_CPU_FIQ));

> > @@ -1664,11 +1694,12 @@ static void finalize_gic_version(VirtMachineState *vms)

> >

> >  static void virt_cpu_post_init(VirtMachineState *vms)

> >  {

> > -    bool aarch64, pmu;

> > +    bool aarch64, pmu, spe;

> >      CPUState *cpu;

> >

> >      aarch64 = object_property_get_bool(OBJECT(first_cpu), "aarch64", NULL);

> >      pmu = object_property_get_bool(OBJECT(first_cpu), "pmu", NULL);

> > +    spe = object_property_get_bool(OBJECT(first_cpu), "spe", NULL);

> >

> >      if (kvm_enabled()) {

> >          CPU_FOREACH(cpu) {

> > @@ -1679,6 +1710,14 @@ static void virt_cpu_post_init(VirtMachineState *vms)

> >                  }

> >                  kvm_arm_pmu_init(cpu);

> >              }

> > +

> > +            if (spe) {

> > +                assert(ARM_CPU(cpu)->has_spe == ON_OFF_AUTO_ON);

> > +                if (kvm_irqchip_in_kernel()) {

> > +                    kvm_arm_spe_set_irq(cpu, PPI(VIRTUAL_SPE_IRQ));

> > +                }

> > +                kvm_arm_spe_init(cpu);

>

> A later patch introduces userspace irqchip support. Should we avoid

> allowing it until then to avoid breaking bisection?

>


Yes, it's possible to break the bisection. To avoid it I think we can
move the above codes
block to a separate patch after adding the userspace irqchip support,
Or, just put the userspace
irqchip support patch before this patch. What's your opinion?

Thanks,
Haibo

> > +            }

> >          }

> >      } else {

> >          if (aarch64 && vms->highmem) {

> > @@ -1927,6 +1966,8 @@ static void machvirt_init(MachineState *machine)

> >

> >      fdt_add_pmu_nodes(vms);

> >

> > +    fdt_add_spe_nodes(vms);

> > +

> >      create_uart(vms, VIRT_UART, sysmem, serial_hd(0));

> >

> >      if (vms->secure) {

> > diff --git a/include/hw/acpi/acpi-defs.h b/include/hw/acpi/acpi-defs.h

> > index 38a42f409a..21e58f27c5 100644

> > --- a/include/hw/acpi/acpi-defs.h

> > +++ b/include/hw/acpi/acpi-defs.h

> > @@ -302,6 +302,9 @@ struct AcpiMadtGenericCpuInterface {

> >      uint32_t vgic_interrupt;

> >      uint64_t gicr_base_address;

> >      uint64_t arm_mpidr;

> > +    uint8_t  efficiency_class;

> > +    uint8_t  reserved2[1];

> > +    uint16_t spe_interrupt; /* ACPI 6.3 */

> >  } QEMU_PACKED;

> >

> >  typedef struct AcpiMadtGenericCpuInterface AcpiMadtGenericCpuInterface;

> > diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h

> > index 72c269aaa5..6013b6d535 100644

> > --- a/include/hw/arm/virt.h

> > +++ b/include/hw/arm/virt.h

> > @@ -49,6 +49,7 @@

> >  #define ARCH_TIMER_NS_EL1_IRQ 14

> >  #define ARCH_TIMER_NS_EL2_IRQ 10

> >

> > +#define VIRTUAL_SPE_IRQ 5

> >  #define VIRTUAL_PMU_IRQ 7

> >

> >  #define PPI(irq) ((irq) + 16)

> > diff --git a/target/arm/cpu.c b/target/arm/cpu.c

> > index f211958eaa..786cc6134c 100644

> > --- a/target/arm/cpu.c

> > +++ b/target/arm/cpu.c

> > @@ -1041,6 +1041,8 @@ static void arm_cpu_initfn(Object *obj)

> >                               "gicv3-maintenance-interrupt", 1);

> >      qdev_init_gpio_out_named(DEVICE(cpu), &cpu->pmu_interrupt,

> >                               "pmu-interrupt", 1);

> > +    qdev_init_gpio_out_named(DEVICE(cpu), &cpu->spe_interrupt,

> > +                             "spe-interrupt", 1);

> >  #endif

> >

> >      /* DTB consumers generally don't in fact care what the 'compatible'

> > diff --git a/target/arm/cpu.h b/target/arm/cpu.h

> > index baf2bbcee8..395a1e5df8 100644

> > --- a/target/arm/cpu.h

> > +++ b/target/arm/cpu.h

> > @@ -800,6 +800,8 @@ struct ARMCPU {

> >      qemu_irq gicv3_maintenance_interrupt;

> >      /* GPIO output for the PMU interrupt */

> >      qemu_irq pmu_interrupt;

> > +    /* GPIO output for the SPE interrupt */

> > +    qemu_irq spe_interrupt;

> >

> >      /* MemoryRegion to use for secure physical accesses */

> >      MemoryRegion *secure_memory;

> > --

> > 2.17.1

> >

> >

>

> Otherwise

>

> Reviewed-by: Andrew Jones <drjones@redhat.com>

>
Andrew Jones Sept. 9, 2020, 9:34 a.m. UTC | #3 
On Wed, Sep 09, 2020 at 03:51:14PM +0800, Haibo Xu wrote:
> > > +

> > > +            if (spe) {

> > > +                assert(ARM_CPU(cpu)->has_spe == ON_OFF_AUTO_ON);

> > > +                if (kvm_irqchip_in_kernel()) {

> > > +                    kvm_arm_spe_set_irq(cpu, PPI(VIRTUAL_SPE_IRQ));

> > > +                }

> > > +                kvm_arm_spe_init(cpu);

> >

> > A later patch introduces userspace irqchip support. Should we avoid

> > allowing it until then to avoid breaking bisection?

> >

> 

> Yes, it's possible to break the bisection. To avoid it I think we can

> move the above codes

> block to a separate patch after adding the userspace irqchip support,

> Or, just put the userspace

> irqchip support patch before this patch. What's your opinion?

>


This patch ca forbid SPE without kernel irqchip. Then the patch that adds
userspace irqchip support would also remove the restriction.

Thanks,
drew
Haibo Xu Sept. 10, 2020, 12:31 a.m. UTC | #4 
On Wed, 9 Sep 2020 at 17:34, Andrew Jones <drjones@redhat.com> wrote:
>

> On Wed, Sep 09, 2020 at 03:51:14PM +0800, Haibo Xu wrote:

> > > > +

> > > > +            if (spe) {

> > > > +                assert(ARM_CPU(cpu)->has_spe == ON_OFF_AUTO_ON);

> > > > +                if (kvm_irqchip_in_kernel()) {

> > > > +                    kvm_arm_spe_set_irq(cpu, PPI(VIRTUAL_SPE_IRQ));

> > > > +                }

> > > > +                kvm_arm_spe_init(cpu);

> > >

> > > A later patch introduces userspace irqchip support. Should we avoid

> > > allowing it until then to avoid breaking bisection?

> > >

> >

> > Yes, it's possible to break the bisection. To avoid it I think we can

> > move the above codes

> > block to a separate patch after adding the userspace irqchip support,

> > Or, just put the userspace

> > irqchip support patch before this patch. What's your opinion?

> >

>

> This patch ca forbid SPE without kernel irqchip. Then the patch that adds

> userspace irqchip support would also remove the restriction.

>

> Thanks,

> drew

>


Good idea! Will fix it in v3.
diff mbox series

Patch

diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
index 9efd7a3881..3fd80fda53 100644
--- a/hw/arm/virt-acpi-build.c
+++ b/hw/arm/virt-acpi-build.c
@@ -665,6 +665,9 @@  build_madt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
         if (arm_feature(&armcpu->env, ARM_FEATURE_PMU)) {
             gicc->performance_interrupt = cpu_to_le32(PPI(VIRTUAL_PMU_IRQ));
         }
+        if (cpu_isar_feature(aa64_spe, armcpu)) {
+            gicc->spe_interrupt = cpu_to_le32(PPI(VIRTUAL_SPE_IRQ));
+        }
         if (vms->virt) {
             gicc->vgic_interrupt = cpu_to_le32(PPI(ARCH_GIC_MAINT_IRQ));
         }
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index 6bacfb668d..bdb1ce925c 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -545,6 +545,32 @@  static void fdt_add_pmu_nodes(const VirtMachineState *vms)
     }
 }
 
+static void fdt_add_spe_nodes(const VirtMachineState *vms)
+{
+    ARMCPU *armcpu = ARM_CPU(first_cpu);
+    uint32_t irqflags = GIC_FDT_IRQ_FLAGS_LEVEL_HI;
+
+    if (!cpu_isar_feature(aa64_spe, armcpu)) {
+        assert(!object_property_get_bool(OBJECT(armcpu), "spe", NULL));
+        return;
+    }
+
+    if (vms->gic_version == VIRT_GIC_VERSION_2) {
+        irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START,
+                             GIC_FDT_IRQ_PPI_CPU_WIDTH,
+                             (1 << vms->smp_cpus) - 1);
+    }
+
+    qemu_fdt_add_subnode(vms->fdt, "/spe");
+    if (arm_feature(&armcpu->env, ARM_FEATURE_V8)) {
+        const char compat[] = "arm,statistical-profiling-extension-v1";
+        qemu_fdt_setprop(vms->fdt, "/spe", "compatible",
+                         compat, sizeof(compat));
+        qemu_fdt_setprop_cells(vms->fdt, "/spe", "interrupts",
+                               GIC_FDT_IRQ_TYPE_PPI, VIRTUAL_SPE_IRQ, irqflags);
+    }
+}
+
 static inline DeviceState *create_acpi_ged(VirtMachineState *vms)
 {
     DeviceState *dev;
@@ -717,6 +743,10 @@  static void create_gic(VirtMachineState *vms)
                                     qdev_get_gpio_in(vms->gic, ppibase
                                                      + VIRTUAL_PMU_IRQ));
 
+        qdev_connect_gpio_out_named(cpudev, "spe-interrupt", 0,
+                                    qdev_get_gpio_in(vms->gic, ppibase
+                                                     + VIRTUAL_SPE_IRQ));
+
         sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ));
         sysbus_connect_irq(gicbusdev, i + smp_cpus,
                            qdev_get_gpio_in(cpudev, ARM_CPU_FIQ));
@@ -1664,11 +1694,12 @@  static void finalize_gic_version(VirtMachineState *vms)
 
 static void virt_cpu_post_init(VirtMachineState *vms)
 {
-    bool aarch64, pmu;
+    bool aarch64, pmu, spe;
     CPUState *cpu;
 
     aarch64 = object_property_get_bool(OBJECT(first_cpu), "aarch64", NULL);
     pmu = object_property_get_bool(OBJECT(first_cpu), "pmu", NULL);
+    spe = object_property_get_bool(OBJECT(first_cpu), "spe", NULL);
 
     if (kvm_enabled()) {
         CPU_FOREACH(cpu) {
@@ -1679,6 +1710,14 @@  static void virt_cpu_post_init(VirtMachineState *vms)
                 }
                 kvm_arm_pmu_init(cpu);
             }
+
+            if (spe) {
+                assert(ARM_CPU(cpu)->has_spe == ON_OFF_AUTO_ON);
+                if (kvm_irqchip_in_kernel()) {
+                    kvm_arm_spe_set_irq(cpu, PPI(VIRTUAL_SPE_IRQ));
+                }
+                kvm_arm_spe_init(cpu);
+            }
         }
     } else {
         if (aarch64 && vms->highmem) {
@@ -1927,6 +1966,8 @@  static void machvirt_init(MachineState *machine)
 
     fdt_add_pmu_nodes(vms);
 
+    fdt_add_spe_nodes(vms);
+
     create_uart(vms, VIRT_UART, sysmem, serial_hd(0));
 
     if (vms->secure) {
diff --git a/include/hw/acpi/acpi-defs.h b/include/hw/acpi/acpi-defs.h
index 38a42f409a..21e58f27c5 100644
--- a/include/hw/acpi/acpi-defs.h
+++ b/include/hw/acpi/acpi-defs.h
@@ -302,6 +302,9 @@  struct AcpiMadtGenericCpuInterface {
     uint32_t vgic_interrupt;
     uint64_t gicr_base_address;
     uint64_t arm_mpidr;
+    uint8_t  efficiency_class;
+    uint8_t  reserved2[1];
+    uint16_t spe_interrupt; /* ACPI 6.3 */
 } QEMU_PACKED;
 
 typedef struct AcpiMadtGenericCpuInterface AcpiMadtGenericCpuInterface;
diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h
index 72c269aaa5..6013b6d535 100644
--- a/include/hw/arm/virt.h
+++ b/include/hw/arm/virt.h
@@ -49,6 +49,7 @@ 
 #define ARCH_TIMER_NS_EL1_IRQ 14
 #define ARCH_TIMER_NS_EL2_IRQ 10
 
+#define VIRTUAL_SPE_IRQ 5
 #define VIRTUAL_PMU_IRQ 7
 
 #define PPI(irq) ((irq) + 16)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index f211958eaa..786cc6134c 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -1041,6 +1041,8 @@  static void arm_cpu_initfn(Object *obj)
                              "gicv3-maintenance-interrupt", 1);
     qdev_init_gpio_out_named(DEVICE(cpu), &cpu->pmu_interrupt,
                              "pmu-interrupt", 1);
+    qdev_init_gpio_out_named(DEVICE(cpu), &cpu->spe_interrupt,
+                             "spe-interrupt", 1);
 #endif
 
     /* DTB consumers generally don't in fact care what the 'compatible'
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index baf2bbcee8..395a1e5df8 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -800,6 +800,8 @@  struct ARMCPU {
     qemu_irq gicv3_maintenance_interrupt;
     /* GPIO output for the PMU interrupt */
     qemu_irq pmu_interrupt;
+    /* GPIO output for the SPE interrupt */
+    qemu_irq spe_interrupt;
 
     /* MemoryRegion to use for secure physical accesses */
     MemoryRegion *secure_memory;