diff mbox series

[V2] cpufreq: Add Zhaoxin/Centaur turbo boost control interface support

Message ID c4f669a8-0da6-862a-0450-ddf178272bdd@zhaoxin.com
State Superseded
Headers show
Series [V2] cpufreq: Add Zhaoxin/Centaur turbo boost control interface support | expand

Commit Message

Tony W Wang-oc June 23, 2022, 1:21 a.m. UTC
Recent Zhaoxin/Centaur CPUs support X86_FEATURE_IDA and the turbo boost
can be dynamically enabled or disabled through MSR 0x1a0[38] in the same
way as Intel. So add turbo boost control support for these CPUs too.

Signed-off-by: Tony W Wang-oc <TonyWWang-oc@zhaoxin.com>
---
  drivers/cpufreq/acpi-cpufreq.c | 4 ++++
  1 file changed, 4 insertions(+)

Comments

Rafael J. Wysocki June 29, 2022, 6:16 p.m. UTC | #1
On Thu, Jun 23, 2022 at 3:21 AM Tony W Wang-oc <TonyWWang-oc@zhaoxin.com> wrote:
>
> Recent Zhaoxin/Centaur CPUs support X86_FEATURE_IDA and the turbo boost
> can be dynamically enabled or disabled through MSR 0x1a0[38] in the same
> way as Intel. So add turbo boost control support for these CPUs too.
>
> Signed-off-by: Tony W Wang-oc <TonyWWang-oc@zhaoxin.com>
> ---
>   drivers/cpufreq/acpi-cpufreq.c | 4 ++++
>   1 file changed, 4 insertions(+)
>
> diff --git a/drivers/cpufreq/acpi-cpufreq.c b/drivers/cpufreq/acpi-cpufreq.c
> index 3d514b8..1bb2b90 100644
> --- a/drivers/cpufreq/acpi-cpufreq.c
> +++ b/drivers/cpufreq/acpi-cpufreq.c
> @@ -78,6 +78,8 @@ static bool boost_state(unsigned int cpu)
>
>         switch (boot_cpu_data.x86_vendor) {
>         case X86_VENDOR_INTEL:
> +       case X86_VENDOR_CENTAUR:
> +       case X86_VENDOR_ZHAOXIN:
>                 rdmsr_on_cpu(cpu, MSR_IA32_MISC_ENABLE, &lo, &hi);
>                 msr = lo | ((u64)hi << 32);
>                 return !(msr & MSR_IA32_MISC_ENABLE_TURBO_DISABLE);
> @@ -97,6 +99,8 @@ static int boost_set_msr(bool enable)
>
>         switch (boot_cpu_data.x86_vendor) {
>         case X86_VENDOR_INTEL:
> +       case X86_VENDOR_CENTAUR:
> +       case X86_VENDOR_ZHAOXIN:
>                 msr_addr = MSR_IA32_MISC_ENABLE;
>                 msr_mask = MSR_IA32_MISC_ENABLE_TURBO_DISABLE;
>                 break;
> --

Applied as 5.20 material.

However, I had to manually fix up the formatting of the patch.

Can you please configure your e-mail client so that this is not
necessary in the future?

Thanks!
diff mbox series

Patch

diff --git a/drivers/cpufreq/acpi-cpufreq.c b/drivers/cpufreq/acpi-cpufreq.c
index 3d514b8..1bb2b90 100644
--- a/drivers/cpufreq/acpi-cpufreq.c
+++ b/drivers/cpufreq/acpi-cpufreq.c
@@ -78,6 +78,8 @@  static bool boost_state(unsigned int cpu)

  	switch (boot_cpu_data.x86_vendor) {
  	case X86_VENDOR_INTEL:
+	case X86_VENDOR_CENTAUR:
+	case X86_VENDOR_ZHAOXIN:
  		rdmsr_on_cpu(cpu, MSR_IA32_MISC_ENABLE, &lo, &hi);
  		msr = lo | ((u64)hi << 32);
  		return !(msr & MSR_IA32_MISC_ENABLE_TURBO_DISABLE);
@@ -97,6 +99,8 @@  static int boost_set_msr(bool enable)

  	switch (boot_cpu_data.x86_vendor) {
  	case X86_VENDOR_INTEL:
+	case X86_VENDOR_CENTAUR:
+	case X86_VENDOR_ZHAOXIN:
  		msr_addr = MSR_IA32_MISC_ENABLE;
  		msr_mask = MSR_IA32_MISC_ENABLE_TURBO_DISABLE;
  		break;