| Message ID | 20220927141504.3886314-6-alex.bennee@linaro.org |
|---|---|
| State | New |
| Headers | show |
| Series | gdbstub/next (MemTxAttrs, re-factoring) | expand |
On 9/27/22 07:14, Alex Bennée wrote: > @@ -2289,8 +2289,8 @@ bool get_phys_addr(CPUARMState *env, target_ulong address, > ARMMMUIdx s1_mmu_idx = stage_1_mmu_idx(mmu_idx); > bool is_secure = regime_is_secure(env, mmu_idx); > > - attrs->requester_type = MEMTXATTRS_CPU; > - attrs->requester_id = env_cpu(env)->cpu_index; > + result->attrs.requester_type = MTRT_CPU; > + result->attrs.requester_id = env_cpu(env)->cpu_index; This hunk shouldn't compile, or the earlier patch shouldn't. I think you have a rebase error in there somewhere. > @@ -280,7 +280,7 @@ static uint64_t arm_ldq_ptw(CPUARMState *env, hwaddr addr, bool is_secure, > ARMMMUIdx mmu_idx, ARMMMUFaultInfo *fi) > { > CPUState *cs = env_cpu(env); > - MemTxAttrs attrs = {}; > + MemTxAttrs attrs = MEMTXATTRS_CPU(cs); > MemTxResult result = MEMTX_OK; > AddressSpace *as; > uint64_t data; Would be handled by a new patch introducing MEMTXATTRS_CPU, as described earlier. r~
diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 4b0dc9bd14..62d32d660a 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -252,7 +252,7 @@ static uint32_t arm_ldl_ptw(CPUARMState *env, hwaddr addr, bool is_secure, ARMMMUIdx mmu_idx, ARMMMUFaultInfo *fi) { CPUState *cs = env_cpu(env); - MemTxAttrs attrs = {}; + MemTxAttrs attrs = MEMTXATTRS_CPU(cs); MemTxResult result = MEMTX_OK; AddressSpace *as; uint32_t data; @@ -280,7 +280,7 @@ static uint64_t arm_ldq_ptw(CPUARMState *env, hwaddr addr, bool is_secure, ARMMMUIdx mmu_idx, ARMMMUFaultInfo *fi) { CPUState *cs = env_cpu(env); - MemTxAttrs attrs = {}; + MemTxAttrs attrs = MEMTXATTRS_CPU(cs); MemTxResult result = MEMTX_OK; AddressSpace *as; uint64_t data; @@ -2289,8 +2289,8 @@ bool get_phys_addr(CPUARMState *env, target_ulong address, ARMMMUIdx s1_mmu_idx = stage_1_mmu_idx(mmu_idx); bool is_secure = regime_is_secure(env, mmu_idx); - attrs->requester_type = MEMTXATTRS_CPU; - attrs->requester_id = env_cpu(env)->cpu_index; + result->attrs.requester_type = MTRT_CPU; + result->attrs.requester_id = env_cpu(env)->cpu_index; if (mmu_idx != s1_mmu_idx) { /*
While mapping your page table base to the GICs address space would be an "interesting" design choice the resultant loads would still be CPU initiated so should be tagged as such. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> --- target/arm/ptw.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-)