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[[PATCH,v2] 7/8] sunxi: usb_phy: setup USB PHY passby for USB0 on H3/H5/A64

Message ID 1515168960-18960-8-git-send-email-jun.nie@linaro.org
State New
Headers show
Series [[PATCH,v2] 7/8] sunxi: usb_phy: setup USB PHY passby for USB0 on H3/H5/A64 | expand

Commit Message

Jun Nie Jan. 5, 2018, 4:15 p.m. UTC 
From: Chen-Yu Tsai <wens@csie.org>

On newer chips, there is a pair of EHCI/OHCI USB hosts for OTG host
mode. USB PHY passby must be configured for its corresponding PHY.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
 arch/arm/mach-sunxi/usb_phy.c | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)
diff mbox series

Patch

diff --git a/arch/arm/mach-sunxi/usb_phy.c b/arch/arm/mach-sunxi/usb_phy.c
index bcf5f15..4ae0a77 100644
--- a/arch/arm/mach-sunxi/usb_phy.c
+++ b/arch/arm/mach-sunxi/usb_phy.c
@@ -245,7 +245,12 @@  void sunxi_usb_phy_init(int index)
 
 	sunxi_usb_phy_config(phy);
 
-	if (phy->id != 0)
+	/*
+	 * Later SoCs such as the H3, H5, A64 have proper hosts for OTG.
+	 * As such the passby settings need to be set for them as well.
+	 */
+	if (phy->id != 0 || IS_ENABLED(CONFIG_MACH_SUNXI_H3_H5) ||
+	    IS_ENABLED(CONFIG_MACH_SUN50I))
 		sunxi_usb_phy_passby(phy, SUNXI_USB_PASSBY_EN);
 
 #ifdef CONFIG_MACH_SUN8I_A83T