diff mbox series

[PULL,42/42] tcg: Improve call argument loading

Message ID	20181225205529.10874-43-richard.henderson@linaro.org
State	Accepted
Commit	4250da10923347c9ee907f8d72bd93dfa5ee8742
Headers	show Delivered-To: patch@linaro.org Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; From: Richard Henderson <richard.henderson@linaro.org> To: qemu-devel@nongnu.org Date: Wed, 26 Dec 2018 07:55:29 +1100 Message-Id: <20181225205529.10874-43-richard.henderson@linaro.org> In-Reply-To: <20181225205529.10874-1-richard.henderson@linaro.org> References: <20181225205529.10874-1-richard.henderson@linaro.org> Subject: [Qemu-devel] [PULL 42/42] tcg: Improve call argument loading Precedence: list Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" <qemu-devel-bounces+patch=linaro.org@nongnu.org>
Series	tcg queued patches \| expand [PULL,00/42] tcg queued patches [PULL,01/42] elf.h: Add the RISCV ELF magic numbers [PULL,02/42] linux-user: Add host dependency for RISC-V 32-bit [PULL,03/42] linux-user: Add host dependency for RISC-V 64-bit [PULL,04/42] exec: Add RISC-V GCC poison macro [PULL,05/42] tcg/riscv: Add the tcg-target.h file [PULL,06/42] tcg/riscv: Add the tcg target registers [PULL,07/42] tcg/riscv: Add support for the constraints [PULL,08/42] tcg/riscv: Add the immediate encoders [PULL,09/42] tcg/riscv: Add the instruction emitters [PULL,10/42] tcg/riscv: Add the relocation functions [PULL,11/42] tcg/riscv: Add the mov and movi instruction [PULL,12/42] tcg/riscv: Add the extract instructions [PULL,13/42] tcg/riscv: Add the out load and store instructions [PULL,14/42] tcg/riscv: Add the add2 and sub2 instructions [PULL,15/42] tcg/riscv: Add branch and jump instructions [PULL,16/42] tcg/riscv: Add slowpath load and store instructions [PULL,17/42] tcg/riscv: Add direct load and store instructions [PULL,18/42] tcg/riscv: Add the out op decoder [PULL,19/42] tcg/riscv: Add the prologue generation and register the JIT [PULL,20/42] tcg/riscv: Add the target init code [PULL,21/42] tcg: Add RISC-V cpu signal handler [PULL,22/42] disas: Add RISC-V support [PULL,23/42] configure: Add support for building RISC-V host [PULL,24/42] disas/microblaze: Remove unused REG_SP macro [PULL,25/42] linux-user: Add safe_syscall for riscv64 host [PULL,26/42] tcg: Renumber TCG_CALL_* flags [PULL,27/42] tcg: Add TCG_CALL_NO_RETURN [PULL,28/42] tcg: Reference count labels [PULL,29/42] tcg: Add reachable_code_pass [PULL,30/42] tcg: Add preferred_reg argument to tcg_reg_alloc [PULL,31/42] tcg: Add preferred_reg argument to temp_load [PULL,32/42] tcg: Add preferred_reg argument to temp_sync [PULL,33/42] tcg: Add preferred_reg argument to tcg_reg_alloc_do_movi [PULL,34/42] tcg: Add output_pref to TCGOp [PULL,35/42] tcg: Improve register allocation for matching constraints [PULL,36/42] tcg: Dump register preference info with liveness [PULL,37/42] tcg: Reindent parts of liveness_pass_1 [PULL,38/42] tcg: Rename and adjust liveness_pass_1 helpers [PULL,39/42] tcg: Split out more subroutines from liveness_pass_1 [PULL,40/42] tcg: Add TCG_OPF_BB_EXIT [PULL,41/42] tcg: Record register preferences during liveness [PULL,42/42] tcg: Improve call argument loading

Commit Message

Richard Henderson Dec. 25, 2018, 8:55 p.m. UTC

Free the argument register only after we have verified that the
temporary is not already in that register.  This case is likely
now that we are back propagating the preferred register.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

---
 tcg/tcg.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

-- 
2.17.2

diff mbox series

Patch

diff --git a/tcg/tcg.c b/tcg/tcg.c
index 5f8c09b0b4..c54b119020 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -3611,15 +3611,16 @@  static void tcg_reg_alloc_call(TCGContext *s, TCGOp *op)
         if (arg != TCG_CALL_DUMMY_ARG) {
             ts = arg_temp(arg);
             reg = tcg_target_call_iarg_regs[i];
-            tcg_reg_free(s, reg, allocated_regs);
 
             if (ts->val_type == TEMP_VAL_REG) {
                 if (ts->reg != reg) {
+                    tcg_reg_free(s, reg, allocated_regs);
                     tcg_out_mov(s, ts->type, reg, ts->reg);
                 }
             } else {
                 TCGRegSet arg_set = 0;
 
+                tcg_reg_free(s, reg, allocated_regs);
                 tcg_regset_set_reg(arg_set, reg);
                 temp_load(s, ts, arg_set, allocated_regs, 0);
             }