diff mbox series

[v6,10/20] target/arm: Simplify set of PSTATE_SS in cpu_get_tb_cpu_state

Message ID 20191011155546.14342-11-richard.henderson@linaro.org
State Superseded
Headers show
Series target/arm: Reduce overhead of cpu_get_tb_cpu_state | expand

Commit Message

Richard Henderson Oct. 11, 2019, 3:55 p.m. UTC
Hoist the variable load for PSTATE into the existing test vs is_a64.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

---
 target/arm/helper.c | 20 ++++++++------------
 1 file changed, 8 insertions(+), 12 deletions(-)

-- 
2.17.1

Comments

Alex Bennée Oct. 14, 2019, 6:21 p.m. UTC | #1
Richard Henderson <richard.henderson@linaro.org> writes:

> Hoist the variable load for PSTATE into the existing test vs is_a64.

>

> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


Reviewed-by: Alex Bennée <alex.bennee@linaro.org>


> ---

>  target/arm/helper.c | 20 ++++++++------------

>  1 file changed, 8 insertions(+), 12 deletions(-)

>

> diff --git a/target/arm/helper.c b/target/arm/helper.c

> index e2a62cf19a..398e5f5d6d 100644

> --- a/target/arm/helper.c

> +++ b/target/arm/helper.c

> @@ -11197,7 +11197,7 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,

>      ARMMMUIdx mmu_idx = arm_mmu_idx(env);

>      int current_el = arm_current_el(env);

>      int fp_el = fp_exception_el(env, current_el);

> -    uint32_t flags;

> +    uint32_t flags, pstate_for_ss;

>

>      if (is_a64(env)) {

>          *pc = env->pc;

> @@ -11205,6 +11205,7 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,

>          if (cpu_isar_feature(aa64_bti, env_archcpu(env))) {

>              flags = FIELD_DP32(flags, TBFLAG_A64, BTYPE, env->btype);

>          }

> +        pstate_for_ss = env->pstate;

>      } else {

>          *pc = env->regs[15];

>

> @@ -11257,9 +11258,11 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,

>              || arm_el_is_aa64(env, 1) || arm_feature(env, ARM_FEATURE_M)) {

>              flags = FIELD_DP32(flags, TBFLAG_A32, VFPEN, 1);

>          }

> +        pstate_for_ss = env->uncached_cpsr;

>      }

>

> -    /* The SS_ACTIVE and PSTATE_SS bits correspond to the state machine

> +    /*

> +     * The SS_ACTIVE and PSTATE_SS bits correspond to the state machine

>       * states defined in the ARM ARM for software singlestep:

>       *  SS_ACTIVE   PSTATE.SS   State

>       *     0            x       Inactive (the TB flag for SS is always 0)

> @@ -11267,16 +11270,9 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,

>       *     1            1       Active-not-pending

>       * SS_ACTIVE is set in hflags; PSTATE_SS is computed every TB.

>       */

> -    if (FIELD_EX32(flags, TBFLAG_ANY, SS_ACTIVE)) {

> -        if (is_a64(env)) {

> -            if (env->pstate & PSTATE_SS) {

> -                flags = FIELD_DP32(flags, TBFLAG_ANY, PSTATE_SS, 1);

> -            }

> -        } else {

> -            if (env->uncached_cpsr & PSTATE_SS) {

> -                flags = FIELD_DP32(flags, TBFLAG_ANY, PSTATE_SS, 1);

> -            }

> -        }

> +    if (FIELD_EX32(flags, TBFLAG_ANY, SS_ACTIVE) &&

> +        (pstate_for_ss & PSTATE_SS)) {

> +        flags = FIELD_DP32(flags, TBFLAG_ANY, PSTATE_SS, 1);

>      }

>

>      *pflags = flags;



--
Alex Bennée
diff mbox series

Patch

diff --git a/target/arm/helper.c b/target/arm/helper.c
index e2a62cf19a..398e5f5d6d 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -11197,7 +11197,7 @@  void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
     ARMMMUIdx mmu_idx = arm_mmu_idx(env);
     int current_el = arm_current_el(env);
     int fp_el = fp_exception_el(env, current_el);
-    uint32_t flags;
+    uint32_t flags, pstate_for_ss;
 
     if (is_a64(env)) {
         *pc = env->pc;
@@ -11205,6 +11205,7 @@  void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
         if (cpu_isar_feature(aa64_bti, env_archcpu(env))) {
             flags = FIELD_DP32(flags, TBFLAG_A64, BTYPE, env->btype);
         }
+        pstate_for_ss = env->pstate;
     } else {
         *pc = env->regs[15];
 
@@ -11257,9 +11258,11 @@  void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
             || arm_el_is_aa64(env, 1) || arm_feature(env, ARM_FEATURE_M)) {
             flags = FIELD_DP32(flags, TBFLAG_A32, VFPEN, 1);
         }
+        pstate_for_ss = env->uncached_cpsr;
     }
 
-    /* The SS_ACTIVE and PSTATE_SS bits correspond to the state machine
+    /*
+     * The SS_ACTIVE and PSTATE_SS bits correspond to the state machine
      * states defined in the ARM ARM for software singlestep:
      *  SS_ACTIVE   PSTATE.SS   State
      *     0            x       Inactive (the TB flag for SS is always 0)
@@ -11267,16 +11270,9 @@  void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
      *     1            1       Active-not-pending
      * SS_ACTIVE is set in hflags; PSTATE_SS is computed every TB.
      */
-    if (FIELD_EX32(flags, TBFLAG_ANY, SS_ACTIVE)) {
-        if (is_a64(env)) {
-            if (env->pstate & PSTATE_SS) {
-                flags = FIELD_DP32(flags, TBFLAG_ANY, PSTATE_SS, 1);
-            }
-        } else {
-            if (env->uncached_cpsr & PSTATE_SS) {
-                flags = FIELD_DP32(flags, TBFLAG_ANY, PSTATE_SS, 1);
-            }
-        }
+    if (FIELD_EX32(flags, TBFLAG_ANY, SS_ACTIVE) &&
+        (pstate_for_ss & PSTATE_SS)) {
+        flags = FIELD_DP32(flags, TBFLAG_ANY, PSTATE_SS, 1);
     }
 
     *pflags = flags;