diff mbox series

[v1,10/15] arm: dts: ns3: add PAXB PCIe host and phy node

Message ID 20200517081945.21282-11-rayagonda.kokatanur@broadcom.com
State New
Headers show
Series add basic driver support for broadcom NS3 soc | expand

Commit Message

Rayagonda Kokatanur May 17, 2020, 8:19 a.m. UTC 
From: Srinath Mannam <srinath.mannam at broadcom.com>

Add PAXB PCIe host controller and phy node for NS3.

Signed-off-by: Srinath Mannam <srinath.mannam at broadcom.com>
Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur at broadcom.com>
---
 arch/arm/dts/ns3-board.dts |  36 +++++++++
 arch/arm/dts/ns3.dtsi      | 158 +++++++++++++++++++++++++++++++++++++
 2 files changed, 194 insertions(+)

Comments

Simon Glass May 25, 2020, 2:14 a.m. UTC | #1 
On Sun, 17 May 2020 at 02:20, Rayagonda Kokatanur
<rayagonda.kokatanur at broadcom.com> wrote:
>
> From: Srinath Mannam <srinath.mannam at broadcom.com>
>
> Add PAXB PCIe host controller and phy node for NS3.
>
> Signed-off-by: Srinath Mannam <srinath.mannam at broadcom.com>
> Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur at broadcom.com>
> ---
>  arch/arm/dts/ns3-board.dts |  36 +++++++++
>  arch/arm/dts/ns3.dtsi      | 158 +++++++++++++++++++++++++++++++++++++
>  2 files changed, 194 insertions(+)

Reviewed-by: Simon Glass <sjg at chromium.org>
diff mbox series

Patch

diff --git a/arch/arm/dts/ns3-board.dts b/arch/arm/dts/ns3-board.dts
index f8e501c225..460ed39132 100644
--- a/arch/arm/dts/ns3-board.dts
+++ b/arch/arm/dts/ns3-board.dts
@@ -67,3 +67,39 @@ 
 &sdio0 {
 	status = "okay";
 };
+
+&pcie0 {
+	status = "okay";
+};
+
+&pcie1 {
+	status = "okay";
+};
+
+&pcie2 {
+	status = "okay";
+};
+
+&pcie3 {
+	status = "okay";
+};
+
+&pcie4 {
+	status = "okay";
+};
+
+&pcie5 {
+	status = "okay";
+};
+
+&pcie6 {
+	status = "okay";
+};
+
+&pcie7 {
+	status = "okay";
+};
+
+&pcie8 {
+	status = "okay";
+};
diff --git a/arch/arm/dts/ns3.dtsi b/arch/arm/dts/ns3.dtsi
index adb1277471..9fd59a855e 100644
--- a/arch/arm/dts/ns3.dtsi
+++ b/arch/arm/dts/ns3.dtsi
@@ -5,6 +5,11 @@ 
 
 #include "skeleton64.dtsi"
 
+#define PCIE_DMA_RANGES dma-ranges = < \
+	0x43000000 0x00 0x80000000 0x00 0x80000000 0x00 0x80000000 \
+	0x43000000 0x08 0x00000000 0x08 0x00000000 0x08 0x00000000 \
+	0x43000000 0x80 0x00000000 0x80 0x00000000 0x80 0x00000000>
+
 / {
 	compatible = "brcm,ns3";
 	#address-cells = <2>;
@@ -89,4 +94,157 @@ 
 					<&pinmux 145 149 6>;
 		};
 	};
+
+	pcie0: pcie at 48000000 {
+		compatible = "brcm,iproc-pcie-paxb-v2";
+		reg = <0 0x48000000 0 0x4000>;
+		bus-range = <0x0 0xff>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+		device_type = "pci";
+		ranges = <0x83000000 0x0 0x42000000 0x0 0x42000000 0 0x2000000>,
+			<0x43000000 0x4 0x00000000 0x4 0x00000000 0 0x80000000>;
+		brcm,pcie-ob;
+		PCIE_DMA_RANGES;
+		phys = <&pcie_phy 0>;
+		phy-names = "pcie-phy";
+		status = "disabled";
+	};
+
+	pcie1: pcie at 48004000 {
+		compatible = "brcm,iproc-pcie-paxb-v2";
+		reg = <0 0x48004000 0 0x4000>;
+		bus-range = <0x0 0xff>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+		device_type = "pci";
+		ranges = <0x83000000 0x0 0x44000000 0x0 0x44000000 0 0x2000000>,
+			<0x43000000 0x4 0x80000000 0x4 0x80000000 0 0x80000000>;
+		brcm,pcie-ob;
+		PCIE_DMA_RANGES;
+		phys = <&pcie_phy 1>;
+		phy-names = "pcie-phy";
+		status = "disabled";
+	};
+
+	pcie2: pcie at 48008000 {
+		compatible = "brcm,iproc-pcie-paxb-v2";
+		reg = <0 0x48008000 0 0x4000>;
+		bus-range = <0x0 0xff>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+		device_type = "pci";
+		ranges = <0x83000000 0x0 0x4a000000 0x0 0x4a000000 0 0x2000000>,
+			<0x43000000 0x5 0x00000000 0x5 0x00000000 0 0x80000000>;
+		brcm,pcie-ob;
+		PCIE_DMA_RANGES;
+		phys = <&pcie_phy 2>;
+		phy-names = "pcie-phy";
+		status = "disabled";
+	};
+
+	pcie3: pcie at 4800c000 {
+		compatible = "brcm,iproc-pcie-paxb-v2";
+		reg = <0 0x4800c000 0 0x4000>;
+		bus-range = <0x0 0xff>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+		device_type = "pci";
+		brcm,pcie-ob;
+		ranges = <0x83000000 0x0 0x4c000000 0x0 0x4c000000 0 0x2000000>,
+			<0x43000000 0x5 0x80000000 0x5 0x80000000 0 0x80000000>;
+		PCIE_DMA_RANGES;
+		phys = <&pcie_phy 3>;
+		phy-names = "pcie-phy";
+		status = "disabled";
+	};
+
+	pcie4: pcie at 48010000 {
+		compatible = "brcm,iproc-pcie-paxb-v2";
+		reg = <0 0x48010000 0 0x4000>;
+		bus-range = <0x0 0xff>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+		device_type = "pci";
+		brcm,pcie-ob;
+		ranges = <0x83000000 0x0 0x52000000 0x0 0x52000000 0 0x2000000>,
+			<0x43000000 0x6 0x00000000 0x6 0x00000000 0 0x80000000>;
+		PCIE_DMA_RANGES;
+		phys = <&pcie_phy 4>;
+		phy-names = "pcie-phy";
+		status = "disabled";
+	};
+
+	pcie5: pcie at 48014000 {
+		compatible = "brcm,iproc-pcie-paxb-v2";
+		reg = <0 0x48014000 0 0x4000>;
+		bus-range = <0x0 0xff>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+		device_type = "pci";
+		brcm,pcie-ob;
+		ranges = <0x83000000 0x0 0x54000000 0x0 0x54000000 0 0x2000000>,
+			<0x43000000 0x6 0x80000000 0x6 0x80000000 0 0x80000000>;
+		PCIE_DMA_RANGES;
+		phys = <&pcie_phy 5>;
+		phy-names = "pcie-phy";
+		status = "disabled";
+	};
+
+	pcie6: pcie at 48018000 {
+		compatible = "brcm,iproc-pcie-paxb-v2";
+		reg = <0 0x48018000 0 0x4000>;
+		bus-range = <0x0 0xff>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+		device_type = "pci";
+		brcm,pcie-ob;
+		ranges = <0x83000000 0x0 0x5a000000 0x0 0x5a000000 0 0x2000000>,
+			<0x43000000 0x7 0x00000000 0x7 0x00000000 0 0x80000000>;
+		PCIE_DMA_RANGES;
+		phys = <&pcie_phy 6>;
+		phy-names = "pcie-phy";
+		status = "disabled";
+	};
+
+	pcie7: pcie at 4801c000 {
+		compatible = "brcm,iproc-pcie-paxb-v2";
+		reg = <0 0x4801c000 0 0x4000>;
+		bus-range = <0x0 0xff>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+		device_type = "pci";
+		brcm,pcie-ob;
+		ranges = <0x83000000 0x0 0x5c000000 0x0 0x5c000000 0 0x2000000>,
+			<0x43000000 0x8 0x00000000 0x8 0x00000000 0 0x80000000>;
+		PCIE_DMA_RANGES;
+		phys = <&pcie_phy 7>;
+		phy-names = "pcie-phy";
+		status = "disabled";
+	};
+
+	pcie8: pcie at 60400000 {
+		compatible = "brcm,iproc-pcie-paxc-v2";
+		reg = <0 0x60400000 0 0x1000>;
+		bus-range = <0x0 0x1>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+		device_type = "pci";
+		ranges = <0x83000000 0 0x10000000 0 0x10000000 0 0x20000000>;
+		status = "disabled";
+		pci at 0,0 {
+			compatible = "pci-bridge";
+			reg = <0x0000 0 0 0 0>;
+		};
+	};
+
+	pcie_phy: phy at 0 {
+		compatible = "brcm,sr-pcie-phy";
+		reg = <0 0x40000000 0 0x200>,
+		      <0 0x6641d000 0 0x100>;
+		reg-names = "reg_base", "cdru_base";
+		#address-cells = <3>;
+		#size-cells = <2>;
+		#phy-cells = <1>;
+	};
 };