@@ -673,11 +673,16 @@ static int vgic_v3_distr_mmio_read(struct vcpu *v, mmio_info_t *info)
case GICD_TYPER:
{
unsigned int irqs = v->domain->arch.vgic.nr_lines + 32;
+ /*
+ * Number of processors that may be used as interrupt targets when ARE
+ * bit is zero. The maximum is 8.
+ */
+ unsigned int ncpus = min_t(unsigned int, v->domain->max_vcpus, 8);
unsigned int order;
if ( dabt.size != DABT_WORD ) goto bad_width;
/* No secure world support for guests. */
- *r = (((v->domain->max_vcpus << 5) & GICD_TYPE_CPUS ) |
+ *r = ((ncpus - 1) << GICD_TYPE_CPUS_SHIFT |
((v->domain->arch.vgic.nr_lines / 32) & GICD_TYPE_LINES));
/*
@@ -93,6 +93,7 @@
#define GICD_CTL_ENABLE 0x1
#define GICD_TYPE_LINES 0x01f
+#define GICD_TYPE_CPUS_SHIFT 5
#define GICD_TYPE_CPUS 0x0e0
#define GICD_TYPE_SEC 0x400
On GICv3, the value (CPUNumber + 1) indicates the number of processor that may be used as interrupts targets when ARE bit is zero. The maximum is 8 processors. Signed-off-by: Julien Grall <julien.grall@linaro.org> --- The current code of the vGIC doesn't support ARE = 0. Nonetheless, the patch is a candidate for backporing to Xen 4.5 to have a consistent vGIC driver. --- xen/arch/arm/vgic-v3.c | 7 ++++++- xen/include/asm-arm/gic.h | 1 + 2 files changed, 7 insertions(+), 1 deletion(-)