diff mbox series

[v3,09/13] target/mips: Reduce mips_tr_breakpoint_check pc advance to 2

Message ID 20210717221851.2124573-10-richard.henderson@linaro.org
State New
Headers show
Series tcg: breakpoint reorg | expand

Commit Message

Richard Henderson July 17, 2021, 10:18 p.m. UTC 
The actual number of bytes advanced need not be 100% exact,
but we should not cross a page when the insn would not.

If mips16 or mips32e are enabled, the minimum insn size is 2.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

---
 target/mips/tcg/translate.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

-- 
2.25.1

Comments

Peter Maydell July 17, 2021, 11:33 p.m. UTC | #1 
On Sat, 17 Jul 2021 at 23:18, Richard Henderson
<richard.henderson@linaro.org> wrote:
>

> The actual number of bytes advanced need not be 100% exact,

> but we should not cross a page when the insn would not.

>

> If mips16 or mips32e are enabled, the minimum insn size is 2.

>

> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

> ---

>  target/mips/tcg/translate.c | 2 +-

>  1 file changed, 1 insertion(+), 1 deletion(-)

>

> diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c

> index fd980ea966..ef00fbd2ac 100644

> --- a/target/mips/tcg/translate.c

> +++ b/target/mips/tcg/translate.c

> @@ -16192,7 +16192,7 @@ static bool mips_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cs,

>       * properly cleared -- thus we increment the PC here so that

>       * the logic setting tb->size below does the right thing.

>       */

> -    ctx->base.pc_next += 4;

> +    ctx->base.pc_next += 2;

>      return true;

>  }

>


Reviewed-by: Peter Maydell <peter.maydell@linaro.org>


thanks
-- PMM
Philippe Mathieu-Daudé July 18, 2021, 7:53 a.m. UTC | #2 
On 7/18/21 12:18 AM, Richard Henderson wrote:
> The actual number of bytes advanced need not be 100% exact,

> but we should not cross a page when the insn would not.

> 

> If mips16 or mips32e are enabled, the minimum insn size is 2.

> 

> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

> ---

>  target/mips/tcg/translate.c | 2 +-

>  1 file changed, 1 insertion(+), 1 deletion(-)


Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
diff mbox series

Patch

diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c
index fd980ea966..ef00fbd2ac 100644
--- a/target/mips/tcg/translate.c
+++ b/target/mips/tcg/translate.c
@@ -16192,7 +16192,7 @@  static bool mips_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cs,
      * properly cleared -- thus we increment the PC here so that
      * the logic setting tb->size below does the right thing.
      */
-    ctx->base.pc_next += 4;
+    ctx->base.pc_next += 2;
     return true;
 }