| Message ID | 20220922145832.1934429-4-alex.bennee@linaro.org |
|---|---|
| State | Superseded |
| Headers | show |
| Series | MemTxAttrs cpu_index and gdbstub/next | expand |
On 9/22/22 14:58, Alex Bennée wrote: > Now that MxTxAttrs encodes a CPU we should use that to figure it out. > This solves edge cases like accessing via gdbstub or qtest. > > Signed-off-by: Alex Bennée<alex.bennee@linaro.org> > Resolves:https://gitlab.com/qemu-project/qemu/-/issues/124 > > --- Reviewed-by: Richard Henderson <richard.henderson@linaro.org> r~
> On 22 Sep 2022, at 16.58, Alex Bennée <alex.bennee@linaro.org> wrote: > > Now that MxTxAttrs encodes a CPU we should use that to figure it out. > This solves edge cases like accessing via gdbstub or qtest. > > Signed-off-by: Alex Bennée <alex.bennee@linaro.org> > Resolves: https://gitlab.com/qemu-project/qemu/-/issues/124 > > --- > v2 > - update for new field > - bool asserts > --- > hw/intc/arm_gic.c | 39 ++++++++++++++++++++++----------------- > 1 file changed, 22 insertions(+), 17 deletions(-) > > diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c > index 492b2421ab..b58d3c4a95 100644 > --- a/hw/intc/arm_gic.c > +++ b/hw/intc/arm_gic.c > @@ -56,17 +56,22 @@ static const uint8_t gic_id_gicv2[] = { > 0x04, 0x00, 0x00, 0x00, 0x90, 0xb4, 0x2b, 0x00, 0x0d, 0xf0, 0x05, 0xb1 > }; > > -static inline int gic_get_current_cpu(GICState *s) > +static inline int gic_get_current_cpu(GICState *s, MemTxAttrs attrs) > { > - if (!qtest_enabled() && s->num_cpu > 1) { > - return current_cpu->cpu_index; > - } > - return 0; > + /* > + * Something other than a CPU accessing the GIC would be a bug as > + * would a CPU index higher than the GICState expects to be > + * handling > + */ > + g_assert(attrs.requester_is_cpu); > + g_assert(attrs.cpu_index < s->num_cpu); > + > + return attrs.requester_id; > } The asserts here abort on macOS, with HVF accelerator: ERROR:../hw/intc/arm_gic.c:66:gic_get_current_cpu: assertion failed: (attrs.requester_is_cpu) Bail out! ERROR:../hw/intc/arm_gic.c:66:gic_get_current_cpu: assertion failed: (attrs.requester_is_cpu) If I revert the changes inside this function, it seemingly works again.
mads@ynddal.dk writes: >> On 22 Sep 2022, at 16.58, Alex Bennée <alex.bennee@linaro.org> wrote: >> >> Now that MxTxAttrs encodes a CPU we should use that to figure it out. >> This solves edge cases like accessing via gdbstub or qtest. >> >> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> >> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/124 >> >> --- >> v2 >> - update for new field >> - bool asserts >> --- >> hw/intc/arm_gic.c | 39 ++++++++++++++++++++++----------------- >> 1 file changed, 22 insertions(+), 17 deletions(-) >> >> diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c >> index 492b2421ab..b58d3c4a95 100644 >> --- a/hw/intc/arm_gic.c >> +++ b/hw/intc/arm_gic.c >> @@ -56,17 +56,22 @@ static const uint8_t gic_id_gicv2[] = { >> 0x04, 0x00, 0x00, 0x00, 0x90, 0xb4, 0x2b, 0x00, 0x0d, 0xf0, 0x05, 0xb1 >> }; >> >> -static inline int gic_get_current_cpu(GICState *s) >> +static inline int gic_get_current_cpu(GICState *s, MemTxAttrs attrs) >> { >> - if (!qtest_enabled() && s->num_cpu > 1) { >> - return current_cpu->cpu_index; >> - } >> - return 0; >> + /* >> + * Something other than a CPU accessing the GIC would be a bug as >> + * would a CPU index higher than the GICState expects to be >> + * handling >> + */ >> + g_assert(attrs.requester_is_cpu); >> + g_assert(attrs.cpu_index < s->num_cpu); >> + >> + return attrs.requester_id; >> } > > The asserts here abort on macOS, with HVF accelerator: > > ERROR:../hw/intc/arm_gic.c:66:gic_get_current_cpu: assertion failed: (attrs.requester_is_cpu) > Bail out! ERROR:../hw/intc/arm_gic.c:66:gic_get_current_cpu: assertion failed: (attrs.requester_is_cpu) > > If I revert the changes inside this function, it seemingly works > again. Thanks for testing. I guess this is because the we have a soft GIC for HVF. Somewhere in the hvf code path we must encode up an MemTxAttrs when the gic is accessed. Could you try in the EC_DATAABORT path in target/arm/hvf/hvf.c:hvf_vcpu_exec: if (iswrite) { val = hvf_get_reg(cpu, srt); address_space_write(&address_space_memory, hvf_exit->exception.physical_address, MEMTXATTRS_CPU(cpu->cpu_index), &val, len); } else { address_space_read(&address_space_memory, hvf_exit->exception.physical_address, MEMTXATTRS_CPU(cpu->cpu_index), &val, len); hvf_set_reg(cpu, srt, val); } if that works I'll cook up a proper patch.
>>> On 22 Sep 2022, at 16.58, Alex Bennée <alex.bennee@linaro.org> wrote: >>> >>> Now that MxTxAttrs encodes a CPU we should use that to figure it out. >>> This solves edge cases like accessing via gdbstub or qtest. >>> >>> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> >>> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/124 >>> >>> --- >>> v2 >>> - update for new field >>> - bool asserts >>> --- >>> hw/intc/arm_gic.c | 39 ++++++++++++++++++++++----------------- >>> 1 file changed, 22 insertions(+), 17 deletions(-) >>> >>> diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c >>> index 492b2421ab..b58d3c4a95 100644 >>> --- a/hw/intc/arm_gic.c >>> +++ b/hw/intc/arm_gic.c >>> @@ -56,17 +56,22 @@ static const uint8_t gic_id_gicv2[] = { >>> 0x04, 0x00, 0x00, 0x00, 0x90, 0xb4, 0x2b, 0x00, 0x0d, 0xf0, 0x05, 0xb1 >>> }; >>> >>> -static inline int gic_get_current_cpu(GICState *s) >>> +static inline int gic_get_current_cpu(GICState *s, MemTxAttrs attrs) >>> { >>> - if (!qtest_enabled() && s->num_cpu > 1) { >>> - return current_cpu->cpu_index; >>> - } >>> - return 0; >>> + /* >>> + * Something other than a CPU accessing the GIC would be a bug as >>> + * would a CPU index higher than the GICState expects to be >>> + * handling >>> + */ >>> + g_assert(attrs.requester_is_cpu); >>> + g_assert(attrs.cpu_index < s->num_cpu); >>> + >>> + return attrs.requester_id; >>> } >> >> The asserts here abort on macOS, with HVF accelerator: >> >> ERROR:../hw/intc/arm_gic.c:66:gic_get_current_cpu: assertion failed: (attrs.requester_is_cpu) >> Bail out! ERROR:../hw/intc/arm_gic.c:66:gic_get_current_cpu: assertion failed: (attrs.requester_is_cpu) >> >> If I revert the changes inside this function, it seemingly works >> again. > > Thanks for testing. > > I guess this is because the we have a soft GIC for HVF. Somewhere in the > hvf code path we must encode up an MemTxAttrs when the gic is accessed. > > Could you try in the EC_DATAABORT path in > target/arm/hvf/hvf.c:hvf_vcpu_exec: > > if (iswrite) { > val = hvf_get_reg(cpu, srt); > address_space_write(&address_space_memory, > hvf_exit->exception.physical_address, > MEMTXATTRS_CPU(cpu->cpu_index), &val, len); > } else { > address_space_read(&address_space_memory, > hvf_exit->exception.physical_address, > MEMTXATTRS_CPU(cpu->cpu_index), &val, len); > hvf_set_reg(cpu, srt, val); > } > > if that works I'll cook up a proper patch. > > -- > Alex Bennée Perfect. This fixes the issue.
diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c index 492b2421ab..b58d3c4a95 100644 --- a/hw/intc/arm_gic.c +++ b/hw/intc/arm_gic.c @@ -56,17 +56,22 @@ static const uint8_t gic_id_gicv2[] = { 0x04, 0x00, 0x00, 0x00, 0x90, 0xb4, 0x2b, 0x00, 0x0d, 0xf0, 0x05, 0xb1 }; -static inline int gic_get_current_cpu(GICState *s) +static inline int gic_get_current_cpu(GICState *s, MemTxAttrs attrs) { - if (!qtest_enabled() && s->num_cpu > 1) { - return current_cpu->cpu_index; - } - return 0; + /* + * Something other than a CPU accessing the GIC would be a bug as + * would a CPU index higher than the GICState expects to be + * handling + */ + g_assert(attrs.requester_is_cpu); + g_assert(attrs.cpu_index < s->num_cpu); + + return attrs.requester_id; } -static inline int gic_get_current_vcpu(GICState *s) +static inline int gic_get_current_vcpu(GICState *s, MemTxAttrs attrs) { - return gic_get_current_cpu(s) + GIC_NCPU; + return gic_get_current_cpu(s, attrs) + GIC_NCPU; } /* Return true if this GIC config has interrupt groups, which is @@ -951,7 +956,7 @@ static uint32_t gic_dist_readb(void *opaque, hwaddr offset, MemTxAttrs attrs) int cm; int mask; - cpu = gic_get_current_cpu(s); + cpu = gic_get_current_cpu(s, attrs); cm = 1 << cpu; if (offset < 0x100) { if (offset == 0) { /* GICD_CTLR */ @@ -1182,7 +1187,7 @@ static void gic_dist_writeb(void *opaque, hwaddr offset, int i; int cpu; - cpu = gic_get_current_cpu(s); + cpu = gic_get_current_cpu(s, attrs); if (offset < 0x100) { if (offset == 0) { if (s->security_extn && !attrs.secure) { @@ -1476,7 +1481,7 @@ static void gic_dist_writel(void *opaque, hwaddr offset, int mask; int target_cpu; - cpu = gic_get_current_cpu(s); + cpu = gic_get_current_cpu(s, attrs); irq = value & 0xf; switch ((value >> 24) & 3) { case 0: @@ -1780,7 +1785,7 @@ static MemTxResult gic_thiscpu_read(void *opaque, hwaddr addr, uint64_t *data, unsigned size, MemTxAttrs attrs) { GICState *s = (GICState *)opaque; - return gic_cpu_read(s, gic_get_current_cpu(s), addr, data, attrs); + return gic_cpu_read(s, gic_get_current_cpu(s, attrs), addr, data, attrs); } static MemTxResult gic_thiscpu_write(void *opaque, hwaddr addr, @@ -1788,7 +1793,7 @@ static MemTxResult gic_thiscpu_write(void *opaque, hwaddr addr, MemTxAttrs attrs) { GICState *s = (GICState *)opaque; - return gic_cpu_write(s, gic_get_current_cpu(s), addr, value, attrs); + return gic_cpu_write(s, gic_get_current_cpu(s, attrs), addr, value, attrs); } /* Wrappers to read/write the GIC CPU interface for a specific CPU. @@ -1818,7 +1823,7 @@ static MemTxResult gic_thisvcpu_read(void *opaque, hwaddr addr, uint64_t *data, { GICState *s = (GICState *)opaque; - return gic_cpu_read(s, gic_get_current_vcpu(s), addr, data, attrs); + return gic_cpu_read(s, gic_get_current_vcpu(s, attrs), addr, data, attrs); } static MemTxResult gic_thisvcpu_write(void *opaque, hwaddr addr, @@ -1827,7 +1832,7 @@ static MemTxResult gic_thisvcpu_write(void *opaque, hwaddr addr, { GICState *s = (GICState *)opaque; - return gic_cpu_write(s, gic_get_current_vcpu(s), addr, value, attrs); + return gic_cpu_write(s, gic_get_current_vcpu(s, attrs), addr, value, attrs); } static uint32_t gic_compute_eisr(GICState *s, int cpu, int lr_start) @@ -1860,7 +1865,7 @@ static uint32_t gic_compute_elrsr(GICState *s, int cpu, int lr_start) static void gic_vmcr_write(GICState *s, uint32_t value, MemTxAttrs attrs) { - int vcpu = gic_get_current_vcpu(s); + int vcpu = gic_get_current_vcpu(s, attrs); uint32_t ctlr; uint32_t abpr; uint32_t bpr; @@ -1995,7 +2000,7 @@ static MemTxResult gic_thiscpu_hyp_read(void *opaque, hwaddr addr, uint64_t *dat { GICState *s = (GICState *)opaque; - return gic_hyp_read(s, gic_get_current_cpu(s), addr, data, attrs); + return gic_hyp_read(s, gic_get_current_cpu(s, attrs), addr, data, attrs); } static MemTxResult gic_thiscpu_hyp_write(void *opaque, hwaddr addr, @@ -2004,7 +2009,7 @@ static MemTxResult gic_thiscpu_hyp_write(void *opaque, hwaddr addr, { GICState *s = (GICState *)opaque; - return gic_hyp_write(s, gic_get_current_cpu(s), addr, value, attrs); + return gic_hyp_write(s, gic_get_current_cpu(s, attrs), addr, value, attrs); } static MemTxResult gic_do_hyp_read(void *opaque, hwaddr addr, uint64_t *data,
Now that MxTxAttrs encodes a CPU we should use that to figure it out. This solves edge cases like accessing via gdbstub or qtest. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/124 --- v2 - update for new field - bool asserts --- hw/intc/arm_gic.c | 39 ++++++++++++++++++++++----------------- 1 file changed, 22 insertions(+), 17 deletions(-)