| Message ID | 20230403-topic-rb1_qcm-v2-3-dae06f8830dc@linaro.org |
|---|---|
| State | Accepted |
| Commit | a64a0192b70cfe7537072ae61a5e0d1d99f976bc |
| Headers | show |
| Series | RB1 + QCM2290 support | expand |
On Wed, Apr 05, 2023 at 05:50:32PM +0200, Konrad Dybcio wrote: > Add an initial device tree for the QCM2290 low-end SoC, featuring 4 > "customized" Cortex-A53 cores and up to 4 GiB of LPDDR(3/4X). > > This revision brings support for: > - TSENS & thermal zones > - SDHCI1/2 > - I2C, SPI, UART > - MPSS > - ADSP > - Wi-Fi > > Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> > --- > arch/arm64/boot/dts/qcom/Makefile | 1 + > arch/arm64/boot/dts/qcom/qcm2290.dtsi | 1561 +++++++++++++++++++++++++++++++++ > 2 files changed, 1562 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile > index 1a29403400b7..6fc8d6664f0c 100644 > --- a/arch/arm64/boot/dts/qcom/Makefile > +++ b/arch/arm64/boot/dts/qcom/Makefile > @@ -70,6 +70,7 @@ dtb-$(CONFIG_ARCH_QCOM) += msm8998-xiaomi-sagit.dtb > dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-1000.dtb > dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-4000.dtb > dtb-$(CONFIG_ARCH_QCOM) += qdu1000-idp.dtb > +dtb-$(CONFIG_ARCH_QCOM) += qrb2210-rb1.dtb I moved this to the patch that actually introduces rb1.dts Thanks, Bjorn > dtb-$(CONFIG_ARCH_QCOM) += qrb5165-rb5.dtb > dtb-$(CONFIG_ARCH_QCOM) += qrb5165-rb5-vision-mezzanine.dtb > dtb-$(CONFIG_ARCH_QCOM) += qru1000-idp.dtb > diff --git a/arch/arm64/boot/dts/qcom/qcm2290.dtsi b/arch/arm64/boot/dts/qcom/qcm2290.dtsi > new file mode 100644 > index 000000000000..ae5abc76bcc7 > --- /dev/null > +++ b/arch/arm64/boot/dts/qcom/qcm2290.dtsi > @@ -0,0 +1,1561 @@ > +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) > +/* > + * Copyright (c) 2023, Linaro Ltd > + * > + * Based on sm6115.dtsi and previous efforts by Shawn Guo & Loic Poulain. > + */ > + > +#include <dt-bindings/clock/qcom,gcc-qcm2290.h> > +#include <dt-bindings/clock/qcom,rpmcc.h> > +#include <dt-bindings/dma/qcom-gpi.h> > +#include <dt-bindings/firmware/qcom,scm.h> > +#include <dt-bindings/gpio/gpio.h> > +#include <dt-bindings/interrupt-controller/arm-gic.h> > +#include <dt-bindings/power/qcom-rpmpd.h> > + > +/ { > + interrupt-parent = <&intc>; > + > + #address-cells = <2>; > + #size-cells = <2>; > + > + chosen { }; > + > + clocks { > + xo_board: xo-board { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + }; > + > + sleep_clk: sleep-clk { > + compatible = "fixed-clock"; > + clock-frequency = <32764>; > + #clock-cells = <0>; > + }; > + }; > + > + cpus { > + #address-cells = <2>; > + #size-cells = <0>; > + > + CPU0: cpu@0 { > + device_type = "cpu"; > + compatible = "arm,cortex-a53"; > + reg = <0x0 0x0>; > + clocks = <&cpufreq_hw 0>; > + capacity-dmips-mhz = <1024>; > + dynamic-power-coefficient = <100>; > + enable-method = "psci"; > + next-level-cache = <&L2_0>; > + qcom,freq-domain = <&cpufreq_hw 0>; > + L2_0: l2-cache { > + compatible = "cache"; > + cache-level = <2>; > + }; > + }; > + > + CPU1: cpu@1 { > + device_type = "cpu"; > + compatible = "arm,cortex-a53"; > + reg = <0x0 0x1>; > + clocks = <&cpufreq_hw 0>; > + capacity-dmips-mhz = <1024>; > + dynamic-power-coefficient = <100>; > + enable-method = "psci"; > + next-level-cache = <&L2_0>; > + qcom,freq-domain = <&cpufreq_hw 0>; > + }; > + > + CPU2: cpu@2 { > + device_type = "cpu"; > + compatible = "arm,cortex-a53"; > + reg = <0x0 0x2>; > + clocks = <&cpufreq_hw 0>; > + capacity-dmips-mhz = <1024>; > + dynamic-power-coefficient = <100>; > + enable-method = "psci"; > + next-level-cache = <&L2_0>; > + qcom,freq-domain = <&cpufreq_hw 0>; > + }; > + > + CPU3: cpu@3 { > + device_type = "cpu"; > + compatible = "arm,cortex-a53"; > + reg = <0x0 0x3>; > + clocks = <&cpufreq_hw 0>; > + capacity-dmips-mhz = <1024>; > + dynamic-power-coefficient = <100>; > + enable-method = "psci"; > + next-level-cache = <&L2_0>; > + qcom,freq-domain = <&cpufreq_hw 0>; > + }; > + > + cpu-map { > + cluster0 { > + core0 { > + cpu = <&CPU0>; > + }; > + > + core1 { > + cpu = <&CPU1>; > + }; > + > + core2 { > + cpu = <&CPU2>; > + }; > + > + core3 { > + cpu = <&CPU3>; > + }; > + }; > + }; > + }; > + > + firmware { > + scm: scm { > + compatible = "qcom,scm-qcm2290", "qcom,scm"; > + clocks = <&rpmcc RPM_SMD_CE1_CLK>; > + clock-names = "core"; > + #reset-cells = <1>; > + }; > + }; > + > + memory@40000000 { > + device_type = "memory"; > + /* We expect the bootloader to fill in the size */ > + reg = <0 0x40000000 0 0>; > + }; > + > + pmu { > + compatible = "arm,armv8-pmuv3"; > + interrupts = <GIC_PPI 6 IRQ_TYPE_LEVEL_HIGH>; > + }; > + > + psci { > + compatible = "arm,psci-1.0"; > + method = "smc"; > + }; > + > + reserved_memory: reserved-memory { > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + > + hyp_mem: hyp@45700000 { > + reg = <0x0 0x45700000 0x0 0x600000>; > + no-map; > + }; > + > + xbl_aop_mem: xbl-aop@45e00000 { > + reg = <0x0 0x45e00000 0x0 0x140000>; > + no-map; > + }; > + > + sec_apps_mem: sec-apps@45fff000 { > + reg = <0x0 0x45fff000 0x0 0x1000>; > + no-map; > + }; > + > + smem_mem: smem@46000000 { > + compatible = "qcom,smem"; > + reg = <0x0 0x46000000 0x0 0x200000>; > + no-map; > + > + hwlocks = <&tcsr_mutex 3>; > + qcom,rpm-msg-ram = <&rpm_msg_ram>; > + }; > + > + pil_modem_mem: modem@4ab00000 { > + reg = <0x0 0x4ab00000 0x0 0x6900000>; > + no-map; > + }; > + > + pil_video_mem: video@51400000 { > + reg = <0x0 0x51400000 0x0 0x500000>; > + no-map; > + }; > + > + wlan_msa_mem: wlan-msa@51900000 { > + reg = <0x0 0x51900000 0x0 0x100000>; > + no-map; > + }; > + > + pil_adsp_mem: adsp@51a00000 { > + reg = <0x0 0x51a00000 0x0 0x1c00000>; > + no-map; > + }; > + > + pil_ipa_fw_mem: ipa-fw@53600000 { > + reg = <0x0 0x53600000 0x0 0x10000>; > + no-map; > + }; > + > + pil_ipa_gsi_mem: ipa-gsi@53610000 { > + reg = <0x0 0x53610000 0x0 0x5000>; > + no-map; > + }; > + > + pil_gpu_mem: zap@53615000 { > + compatible = "shared-dma-pool"; > + reg = <0x0 0x53615000 0x0 0x2000>; > + no-map; > + }; > + > + cont_splash_memory: framebuffer@5c000000 { > + reg = <0x0 0x5c000000 0x0 0x00f00000>; > + no-map; > + }; > + > + dfps_data_memory: dpfs-data@5cf00000 { > + reg = <0x0 0x5cf00000 0x0 0x0100000>; > + no-map; > + }; > + > + removed_mem: reserved@60000000 { > + reg = <0x0 0x60000000 0x0 0x3900000>; > + no-map; > + }; > + > + rmtfs_mem: memory@89b01000 { > + compatible = "qcom,rmtfs-mem"; > + reg = <0x0 0x89b01000 0x0 0x200000>; > + no-map; > + > + qcom,client-id = <1>; > + qcom,vmid = <QCOM_SCM_VMID_MSS_MSA QCOM_SCM_VMID_NAV>; > + }; > + }; > + > + rpm-glink { > + compatible = "qcom,glink-rpm"; > + interrupts = <GIC_SPI 194 IRQ_TYPE_EDGE_RISING>; > + qcom,rpm-msg-ram = <&rpm_msg_ram>; > + mboxes = <&apcs_glb 0>; > + > + rpm_requests: rpm-requests { > + compatible = "qcom,rpm-qcm2290"; > + qcom,glink-channels = "rpm_requests"; > + > + rpmcc: clock-controller { > + compatible = "qcom,rpmcc-qcm2290", "qcom,rpmcc"; > + clocks = <&xo_board>; > + clock-names = "xo"; > + #clock-cells = <1>; > + }; > + > + rpmpd: power-controller { > + compatible = "qcom,qcm2290-rpmpd"; > + #power-domain-cells = <1>; > + operating-points-v2 = <&rpmpd_opp_table>; > + > + rpmpd_opp_table: opp-table { > + compatible = "operating-points-v2"; > + > + rpmpd_opp_min_svs: opp1 { > + opp-level = <RPM_SMD_LEVEL_MIN_SVS>; > + }; > + > + rpmpd_opp_low_svs: opp2 { > + opp-level = <RPM_SMD_LEVEL_LOW_SVS>; > + }; > + > + rpmpd_opp_svs: opp3 { > + opp-level = <RPM_SMD_LEVEL_SVS>; > + }; > + > + rpmpd_opp_svs_plus: opp4 { > + opp-level = <RPM_SMD_LEVEL_SVS_PLUS>; > + }; > + > + rpmpd_opp_nom: opp5 { > + opp-level = <RPM_SMD_LEVEL_NOM>; > + }; > + > + rpmpd_opp_nom_plus: opp6 { > + opp-level = <RPM_SMD_LEVEL_NOM_PLUS>; > + }; > + > + rpmpd_opp_turbo: opp7 { > + opp-level = <RPM_SMD_LEVEL_TURBO>; > + }; > + > + rpmpd_opp_turbo_plus: opp8 { > + opp-level = <RPM_SMD_LEVEL_TURBO_NO_CPR>; > + }; > + }; > + }; > + }; > + }; > + > + smp2p-adsp { > + compatible = "qcom,smp2p"; > + qcom,smem = <443>, <429>; > + > + interrupts = <GIC_SPI 279 IRQ_TYPE_EDGE_RISING>; > + > + mboxes = <&apcs_glb 10>; > + > + qcom,local-pid = <0>; > + qcom,remote-pid = <2>; > + > + adsp_smp2p_out: master-kernel { > + qcom,entry-name = "master-kernel"; > + #qcom,smem-state-cells = <1>; > + }; > + > + adsp_smp2p_in: slave-kernel { > + qcom,entry-name = "slave-kernel"; > + interrupt-controller; > + #interrupt-cells = <2>; > + }; > + }; > + > + smp2p-mpss { > + compatible = "qcom,smp2p"; > + qcom,smem = <435>, <428>; > + > + interrupts = <GIC_SPI 70 IRQ_TYPE_EDGE_RISING>; > + > + mboxes = <&apcs_glb 14>; > + > + qcom,local-pid = <0>; > + qcom,remote-pid = <1>; > + > + modem_smp2p_out: master-kernel { > + qcom,entry-name = "master-kernel"; > + #qcom,smem-state-cells = <1>; > + }; > + > + modem_smp2p_in: slave-kernel { > + qcom,entry-name = "slave-kernel"; > + interrupt-controller; > + #interrupt-cells = <2>; > + }; > + > + wlan_smp2p_in: wlan-wpss-to-ap { > + qcom,entry-name = "wlan"; > + interrupt-controller; > + #interrupt-cells = <2>; > + }; > + }; > + > + soc: soc@0 { > + compatible = "simple-bus"; > + #address-cells = <2>; > + #size-cells = <2>; > + ranges = <0 0 0 0 0x10 0>; > + dma-ranges = <0 0 0 0 0x10 0>; > + > + tcsr_mutex: hwlock@340000 { > + compatible = "qcom,tcsr-mutex"; > + reg = <0x0 0x00340000 0x0 0x20000>; > + #hwlock-cells = <1>; > + }; > + > + tlmm: pinctrl@500000 { > + compatible = "qcom,qcm2290-tlmm"; > + reg = <0x0 0x00500000 0x0 0x300000>; > + interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; > + gpio-controller; > + gpio-ranges = <&tlmm 0 0 127>; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + > + qup_i2c0_default: qup-i2c0-default-state { > + pins = "gpio0", "gpio1"; > + function = "qup0"; > + drive-strength = <2>; > + bias-pull-up; > + }; > + > + qup_i2c1_default: qup-i2c1-default-state { > + pins = "gpio4", "gpio5"; > + function = "qup1"; > + drive-strength = <2>; > + bias-pull-up; > + }; > + > + qup_i2c2_default: qup-i2c2-default-state { > + pins = "gpio6", "gpio7"; > + function = "qup2"; > + drive-strength = <2>; > + bias-pull-up; > + }; > + > + qup_i2c3_default: qup-i2c3-default-state { > + pins = "gpio8", "gpio9"; > + function = "qup3"; > + drive-strength = <2>; > + bias-pull-up; > + }; > + > + qup_i2c4_default: qup-i2c4-default-state { > + pins = "gpio12", "gpio13"; > + function = "qup4"; > + drive-strength = <2>; > + bias-pull-up; > + }; > + > + qup_i2c5_default: qup-i2c5-default-state { > + pins = "gpio14", "gpio15"; > + function = "qup5"; > + drive-strength = <2>; > + bias-pull-up; > + }; > + > + qup_spi0_default: qup-spi0-default-state { > + pins = "gpio0", "gpio1","gpio2", "gpio3"; > + function = "qup0"; > + drive-strength = <2>; > + bias-pull-up; > + }; > + > + qup_spi1_default: qup-spi1-default-state { > + pins = "gpio4", "gpio5", "gpio69", "gpio70"; > + function = "qup1"; > + drive-strength = <2>; > + bias-pull-up; > + }; > + > + qup_spi2_default: qup-spi2-default-state { > + pins = "gpio6", "gpio7", "gpio71", "gpio80"; > + function = "qup2"; > + drive-strength = <2>; > + bias-pull-up; > + }; > + > + qup_spi3_default: qup-spi3-default-state { > + pins = "gpio8", "gpio9", "gpio10", "gpio11"; > + function = "qup3"; > + drive-strength = <2>; > + bias-pull-up; > + }; > + > + qup_spi4_default: qup-spi4-default-state { > + pins = "gpio12", "gpio13", "gpio96", "gpio97"; > + function = "qup4"; > + drive-strength = <2>; > + bias-pull-up; > + }; > + > + qup_spi5_default: qup-spi5-default-state { > + pins = "gpio14", "gpio15", "gpio16", "gpio17"; > + function = "qup5"; > + drive-strength = <2>; > + bias-pull-up; > + }; > + > + qup_uart0_default: qup-uart0-default-state { > + pins = "gpio0", "gpio1", "gpio2", "gpio3"; > + function = "qup0"; > + drive-strength = <2>; > + bias-disable; > + }; > + > + qup_uart4_default: qup-uart4-default-state { > + pins = "gpio12", "gpio13"; > + function = "qup4"; > + drive-strength = <2>; > + bias-disable; > + }; > + > + sdc1_state_on: sdc1-on-state { > + clk-pins { > + pins = "sdc1_clk"; > + drive-strength = <16>; > + bias-disable; > + }; > + > + cmd-pins { > + pins = "sdc1_cmd"; > + drive-strength = <10>; > + bias-pull-up; > + }; > + > + data-pins { > + pins = "sdc1_data"; > + drive-strength = <10>; > + bias-pull-up; > + }; > + > + rclk-pins { > + pins = "sdc1_rclk"; > + bias-pull-down; > + }; > + }; > + > + sdc1_state_off: sdc1-off-state { > + clk-pins { > + pins = "sdc1_clk"; > + drive-strength = <2>; > + bias-disable; > + }; > + > + cmd-pins { > + pins = "sdc1_cmd"; > + drive-strength = <2>; > + bias-pull-up; > + }; > + > + data-pins { > + pins = "sdc1_data"; > + drive-strength = <2>; > + bias-pull-up; > + }; > + > + rclk-pins { > + pins = "sdc1_rclk"; > + bias-pull-down; > + }; > + }; > + > + sdc2_state_on: sdc2-on-state { > + clk-pins { > + pins = "sdc2_clk"; > + drive-strength = <16>; > + bias-disable; > + }; > + > + cmd-pins { > + pins = "sdc2_cmd"; > + drive-strength = <10>; > + bias-pull-up; > + }; > + > + data-pins { > + pins = "sdc2_data"; > + drive-strength = <10>; > + bias-pull-up; > + }; > + }; > + > + sdc2_state_off: sdc2-off-state { > + clk-pins { > + pins = "sdc2_clk"; > + drive-strength = <2>; > + bias-disable; > + }; > + > + cmd-pins { > + pins = "sdc2_cmd"; > + drive-strength = <2>; > + bias-pull-up; > + }; > + > + data-pins { > + pins = "sdc2_data"; > + drive-strength = <2>; > + bias-pull-up; > + }; > + }; > + }; > + > + gcc: clock-controller@1400000 { > + compatible = "qcom,gcc-qcm2290"; > + reg = <0x0 0x01400000 0x0 0x1f0000>; > + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&sleep_clk>; > + clock-names = "bi_tcxo", "sleep_clk"; > + #clock-cells = <1>; > + #reset-cells = <1>; > + #power-domain-cells = <1>; > + }; > + > + usb_hsphy: phy@1613000 { > + compatible = "qcom,qcm2290-qusb2-phy"; > + reg = <0x0 0x01613000 0x0 0x180>; > + > + clocks = <&gcc GCC_AHB2PHY_USB_CLK>, > + <&rpmcc RPM_SMD_XO_CLK_SRC>; > + clock-names = "cfg_ahb", "ref"; > + > + resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; > + nvmem-cells = <&qusb2_hstx_trim>; > + #phy-cells = <0>; > + > + status = "disabled"; > + }; > + > + qfprom@1b44000 { > + compatible = "qcom,qcm2290-qfprom", "qcom,qfprom"; > + reg = <0x0 0x01b44000 0x0 0x3000>; > + #address-cells = <1>; > + #size-cells = <1>; > + > + qusb2_hstx_trim: hstx-trim@25b { > + reg = <0x25b 0x1>; > + bits = <1 4>; > + }; > + }; > + > + spmi_bus: spmi@1c40000 { > + compatible = "qcom,spmi-pmic-arb"; > + reg = <0x0 0x01c40000 0x0 0x1100>, > + <0x0 0x01e00000 0x0 0x2000000>, > + <0x0 0x03e00000 0x0 0x100000>, > + <0x0 0x03f00000 0x0 0xa0000>, > + <0x0 0x01c0a000 0x0 0x26000>; > + reg-names = "core", > + "chnls", > + "obsrvr", > + "intr", > + "cnfg"; > + interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-names = "periph_irq"; > + qcom,ee = <0>; > + qcom,channel = <0>; > + #address-cells = <2>; > + #size-cells = <0>; > + interrupt-controller; > + #interrupt-cells = <4>; > + }; > + > + tsens0: thermal-sensor@4411000 { > + compatible = "qcom,qcm2290-tsens", "qcom,tsens-v2"; > + reg = <0x0 0x04411000 0x0 0x1ff>, > + <0x0 0x04410000 0x0 0x8>; > + #qcom,sensors = <10>; > + interrupts = <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-names = "uplow", "critical"; > + #thermal-sensor-cells = <1>; > + }; > + > + rng: rng@4453000 { > + compatible = "qcom,prng-ee"; > + reg = <0x0 0x04453000 0x0 0x1000>; > + clocks = <&rpmcc RPM_SMD_HWKM_CLK>; > + clock-names = "core"; > + }; > + > + rpm_msg_ram: sram@45f0000 { > + compatible = "qcom,rpm-msg-ram"; > + reg = <0x0 0x045f0000 0x0 0x7000>; > + }; > + > + sram@4690000 { > + compatible = "qcom,rpm-stats"; > + reg = <0x0 0x04690000 0x0 0x10000>; > + }; > + > + sdhc_1: mmc@4744000 { > + compatible = "qcom,qcm2290-sdhci", "qcom,sdhci-msm-v5"; > + reg = <0x0 0x04744000 0x0 0x1000>, > + <0x0 0x04745000 0x0 0x1000>, > + <0x0 0x04748000 0x0 0x8000>; > + reg-names = "hc", > + "cqhci", > + "ice"; > + > + interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-names = "hc_irq", "pwr_irq"; > + > + clocks = <&gcc GCC_SDCC1_AHB_CLK>, > + <&gcc GCC_SDCC1_APPS_CLK>, > + <&rpmcc RPM_SMD_XO_CLK_SRC>, > + <&gcc GCC_SDCC1_ICE_CORE_CLK>; > + clock-names = "iface", > + "core", > + "xo", > + "ice"; > + > + resets = <&gcc GCC_SDCC1_BCR>; > + > + power-domains = <&rpmpd QCM2290_VDDCX>; > + iommus = <&apps_smmu 0xc0 0x0>; > + > + qcom,dll-config = <0x000f642c>; > + qcom,ddr-config = <0x80040868>; > + bus-width = <8>; > + > + status = "disabled"; > + }; > + > + sdhc_2: mmc@4784000 { > + compatible = "qcom,qcm2290-sdhci", "qcom,sdhci-msm-v5"; > + reg = <0x0 0x04784000 0x0 0x1000>; > + reg-names = "hc"; > + > + interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-names = "hc_irq", "pwr_irq"; > + > + clocks = <&gcc GCC_SDCC2_AHB_CLK>, > + <&gcc GCC_SDCC2_APPS_CLK>, > + <&rpmcc RPM_SMD_XO_CLK_SRC>; > + clock-names = "iface", > + "core", > + "xo"; > + > + resets = <&gcc GCC_SDCC2_BCR>; > + > + power-domains = <&rpmpd QCM2290_VDDCX>; > + operating-points-v2 = <&sdhc2_opp_table>; > + iommus = <&apps_smmu 0xa0 0x0>; > + > + qcom,dll-config = <0x0007642c>; > + qcom,ddr-config = <0x80040868>; > + bus-width = <4>; > + > + status = "disabled"; > + > + sdhc2_opp_table: opp-table { > + compatible = "operating-points-v2"; > + > + opp-100000000 { > + opp-hz = /bits/ 64 <100000000>; > + required-opps = <&rpmpd_opp_low_svs>; > + }; > + > + opp-202000000 { > + opp-hz = /bits/ 64 <202000000>; > + required-opps = <&rpmpd_opp_svs_plus>; > + }; > + }; > + }; > + > + gpi_dma0: dma-controller@4a00000 { > + compatible = "qcom,qcm2290-gpi-dma", "qcom,sm6350-gpi-dma"; > + reg = <0x0 0x04a00000 0x0 0x60000>; > + interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>; > + dma-channels = <10>; > + dma-channel-mask = <0x1f>; > + iommus = <&apps_smmu 0xf6 0x0>; > + #dma-cells = <3>; > + status = "disabled"; > + }; > + > + qupv3_id_0: geniqup@4ac0000 { > + compatible = "qcom,geni-se-qup"; > + reg = <0x0 0x04ac0000 0x0 0x2000>; > + clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, > + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; > + clock-names = "m-ahb", "s-ahb"; > + iommus = <&apps_smmu 0xe3 0x0>; > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + status = "disabled"; > + > + i2c0: i2c@4a80000 { > + compatible = "qcom,geni-i2c"; > + reg = <0x0 0x04a80000 0x0 0x4000>; > + interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; > + clock-names = "se"; > + pinctrl-0 = <&qup_i2c0_default>; > + pinctrl-names = "default"; > + dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, > + <&gpi_dma0 1 0 QCOM_GPI_I2C>; > + dma-names = "tx", "rx"; > + #address-cells = <1>; > + #size-cells = <0>; > + status = "disabled"; > + }; > + > + spi0: spi@4a80000 { > + compatible = "qcom,geni-spi"; > + reg = <0x0 0x04a80000 0x0 0x4000>; > + interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; > + clock-names = "se"; > + pinctrl-0 = <&qup_spi0_default>; > + pinctrl-names = "default"; > + dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, > + <&gpi_dma0 1 0 QCOM_GPI_SPI>; > + dma-names = "tx", "rx"; > + #address-cells = <1>; > + #size-cells = <0>; > + status = "disabled"; > + }; > + > + uart0: serial@4a80000 { > + compatible = "qcom,geni-uart"; > + reg = <0x0 0x04a80000 0x0 0x4000>; > + interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; > + clock-names = "se"; > + pinctrl-0 = <&qup_uart0_default>; > + pinctrl-names = "default"; > + status = "disabled"; > + }; > + > + i2c1: i2c@4a84000 { > + compatible = "qcom,geni-i2c"; > + reg = <0x0 0x04a84000 0x0 0x4000>; > + interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; > + clock-names = "se"; > + pinctrl-0 = <&qup_i2c1_default>; > + pinctrl-names = "default"; > + dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, > + <&gpi_dma0 1 1 QCOM_GPI_I2C>; > + dma-names = "tx", "rx"; > + #address-cells = <1>; > + #size-cells = <0>; > + status = "disabled"; > + }; > + > + spi1: spi@4a84000 { > + compatible = "qcom,geni-spi"; > + reg = <0x0 0x04a84000 0x0 0x4000>; > + interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; > + clock-names = "se"; > + pinctrl-0 = <&qup_spi1_default>; > + pinctrl-names = "default"; > + dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, > + <&gpi_dma0 1 1 QCOM_GPI_SPI>; > + dma-names = "tx", "rx"; > + #address-cells = <1>; > + #size-cells = <0>; > + status = "disabled"; > + }; > + > + i2c2: i2c@4a88000 { > + compatible = "qcom,geni-i2c"; > + reg = <0x0 0x04a88000 0x0 0x4000>; > + interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; > + clock-names = "se"; > + pinctrl-0 = <&qup_i2c2_default>; > + pinctrl-names = "default"; > + dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, > + <&gpi_dma0 1 2 QCOM_GPI_I2C>; > + dma-names = "tx", "rx"; > + #address-cells = <1>; > + #size-cells = <0>; > + status = "disabled"; > + }; > + > + spi2: spi@4a88000 { > + compatible = "qcom,geni-spi"; > + reg = <0x0 0x04a88000 0x0 0x4000>; > + interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; > + clock-names = "se"; > + pinctrl-0 = <&qup_spi2_default>; > + pinctrl-names = "default"; > + dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, > + <&gpi_dma0 1 2 QCOM_GPI_SPI>; > + dma-names = "tx", "rx"; > + #address-cells = <1>; > + #size-cells = <0>; > + status = "disabled"; > + }; > + > + i2c3: i2c@4a8c000 { > + compatible = "qcom,geni-i2c"; > + reg = <0x0 0x04a8c000 0x0 0x4000>; > + interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; > + clock-names = "se"; > + pinctrl-0 = <&qup_i2c3_default>; > + pinctrl-names = "default"; > + dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, > + <&gpi_dma0 1 3 QCOM_GPI_I2C>; > + dma-names = "tx", "rx"; > + #address-cells = <1>; > + #size-cells = <0>; > + status = "disabled"; > + }; > + > + spi3: spi@4a8c000 { > + compatible = "qcom,geni-spi"; > + reg = <0x0 0x04a8c000 0x0 0x4000>; > + interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; > + clock-names = "se"; > + pinctrl-0 = <&qup_spi3_default>; > + pinctrl-names = "default"; > + dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, > + <&gpi_dma0 1 3 QCOM_GPI_SPI>; > + dma-names = "tx", "rx"; > + #address-cells = <1>; > + #size-cells = <0>; > + status = "disabled"; > + }; > + > + i2c4: i2c@4a90000 { > + compatible = "qcom,geni-i2c"; > + reg = <0x0 0x04a90000 0x0 0x4000>; > + interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; > + clock-names = "se"; > + pinctrl-0 = <&qup_i2c4_default>; > + pinctrl-names = "default"; > + dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, > + <&gpi_dma0 1 4 QCOM_GPI_I2C>; > + dma-names = "tx", "rx"; > + #address-cells = <1>; > + #size-cells = <0>; > + status = "disabled"; > + }; > + > + spi4: spi@4a90000 { > + compatible = "qcom,geni-spi"; > + reg = <0x0 0x04a90000 0x0 0x4000>; > + interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>; > + clock-names = "se"; > + clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; > + pinctrl-names = "default"; > + pinctrl-0 = <&qup_spi4_default>; > + dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, > + <&gpi_dma0 1 4 QCOM_GPI_SPI>; > + dma-names = "tx", "rx"; > + #address-cells = <1>; > + #size-cells = <0>; > + status = "disabled"; > + }; > + > + uart4: serial@4a90000 { > + compatible = "qcom,geni-uart"; > + reg = <0x0 0x04a90000 0x0 0x4000>; > + interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; > + clock-names = "se"; > + pinctrl-0 = <&qup_uart4_default>; > + pinctrl-names = "default"; > + status = "disabled"; > + }; > + > + i2c5: i2c@4a94000 { > + compatible = "qcom,geni-i2c"; > + reg = <0x0 0x04a94000 0x0 0x4000>; > + interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; > + clock-names = "se"; > + pinctrl-0 = <&qup_i2c5_default>; > + pinctrl-names = "default"; > + dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, > + <&gpi_dma0 1 5 QCOM_GPI_I2C>; > + dma-names = "tx", "rx"; > + #address-cells = <1>; > + #size-cells = <0>; > + status = "disabled"; > + }; > + > + spi5: spi@4a94000 { > + compatible = "qcom,geni-spi"; > + reg = <0x0 0x04a94000 0x0 0x4000>; > + interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; > + clock-names = "se"; > + pinctrl-0 = <&qup_spi5_default>; > + pinctrl-names = "default"; > + dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, > + <&gpi_dma0 1 5 QCOM_GPI_SPI>; > + dma-names = "tx", "rx"; > + #address-cells = <1>; > + #size-cells = <0>; > + status = "disabled"; > + }; > + }; > + > + usb: usb@4ef8800 { > + compatible = "qcom,qcm2290-dwc3", "qcom,dwc3"; > + reg = <0x0 0x04ef8800 0x0 0x400>; > + interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-names = "hs_phy_irq", "ss_phy_irq"; > + > + clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, > + <&gcc GCC_USB30_PRIM_MASTER_CLK>, > + <&gcc GCC_SYS_NOC_USB3_PRIM_AXI_CLK>, > + <&gcc GCC_USB30_PRIM_SLEEP_CLK>, > + <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, > + <&gcc GCC_USB3_PRIM_CLKREF_CLK>; > + clock-names = "cfg_noc", > + "core", > + "iface", > + "sleep", > + "mock_utmi", > + "xo"; > + > + assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, > + <&gcc GCC_USB30_PRIM_MASTER_CLK>; > + assigned-clock-rates = <19200000>, <133333333>; > + > + resets = <&gcc GCC_USB30_PRIM_BCR>; > + power-domains = <&gcc GCC_USB30_PRIM_GDSC>; > + wakeup-source; > + > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + > + status = "disabled"; > + > + usb_dwc3: usb@4e00000 { > + compatible = "snps,dwc3"; > + reg = <0x0 0x04e00000 0x0 0xcd00>; > + interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; > + phys = <&usb_hsphy>; > + phy-names = "usb2-phy"; > + iommus = <&apps_smmu 0x120 0x0>; > + snps,dis_u2_susphy_quirk; > + snps,dis_enblslpm_quirk; > + snps,has-lpm-erratum; > + snps,hird-threshold = /bits/ 8 <0x10>; > + snps,usb3_lpm_capable; > + maximum-speed = "super-speed"; > + dr_mode = "otg"; > + }; > + }; > + > + remoteproc_mpss: remoteproc@6080000 { > + compatible = "qcom,qcm2290-mpss-pas", "qcom,sm6115-mpss-pas"; > + reg = <0x0 0x06080000 0x0 0x100>; > + > + interrupts-extended = <&intc GIC_SPI 307 IRQ_TYPE_EDGE_RISING>, > + <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, > + <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, > + <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, > + <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, > + <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; > + interrupt-names = "wdog", > + "fatal", > + "ready", > + "handover", > + "stop-ack", > + "shutdown-ack"; > + > + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; > + clock-names = "xo"; > + > + power-domains = <&rpmpd QCM2290_VDDCX>; > + > + memory-region = <&pil_modem_mem>; > + > + qcom,smem-states = <&modem_smp2p_out 0>; > + qcom,smem-state-names = "stop"; > + > + status = "disabled"; > + > + glink-edge { > + interrupts = <GIC_SPI 68 IRQ_TYPE_EDGE_RISING>; > + label = "mpss"; > + qcom,remote-pid = <1>; > + mboxes = <&apcs_glb 12>; > + }; > + }; > + > + remoteproc_adsp: remoteproc@ab00000 { > + compatible = "qcom,qcm2290-adsp-pas", "qcom,sm6115-adsp-pas"; > + reg = <0x0 0x0ab00000 0x0 0x100>; > + > + interrupts-extended = <&intc GIC_SPI 282 IRQ_TYPE_EDGE_RISING>, > + <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, > + <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, > + <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, > + <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; > + interrupt-names = "wdog", > + "fatal", > + "ready", > + "handover", > + "stop-ack"; > + > + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; > + clock-names = "xo"; > + > + power-domains = <&rpmpd QCM2290_VDD_LPI_CX>, > + <&rpmpd QCM2290_VDD_LPI_MX>; > + > + memory-region = <&pil_adsp_mem>; > + > + qcom,smem-states = <&adsp_smp2p_out 0>; > + qcom,smem-state-names = "stop"; > + > + status = "disabled"; > + > + glink-edge { > + interrupts = <GIC_SPI 277 IRQ_TYPE_EDGE_RISING>; > + label = "lpass"; > + qcom,remote-pid = <2>; > + mboxes = <&apcs_glb 8>; > + }; > + }; > + > + apps_smmu: iommu@c600000 { > + compatible = "qcom,qcm2290-smmu-500", "qcom,smmu-500", "arm,mmu-500"; > + reg = <0x0 0x0c600000 0x0 0x80000>; > + #iommu-cells = <2>; > + #global-interrupts = <1>; > + > + interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; > + }; > + > + wifi: wifi@c800000 { > + compatible = "qcom,wcn3990-wifi"; > + reg = <0x0 0x0c800000 0x0 0x800000>; > + reg-names = "membase"; > + memory-region = <&wlan_msa_mem>; > + interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; > + iommus = <&apps_smmu 0x1a0 0x1>; > + qcom,msa-fixed-perm; > + status = "disabled"; > + }; > + > + watchdog@f017000 { > + compatible = "qcom,apss-wdt-qcm2290", "qcom,kpss-wdt"; > + reg = <0x0 0x0f017000 0x0 0x1000>; > + interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>, > + <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&sleep_clk>; > + }; > + > + apcs_glb: mailbox@f111000 { > + compatible = "qcom,qcm2290-apcs-hmss-global"; > + reg = <0x0 0x0f111000 0x0 0x1000>; > + #mbox-cells = <1>; > + }; > + > + timer@f120000 { > + compatible = "arm,armv7-timer-mem"; > + reg = <0x0 0x0f120000 0x0 0x1000>; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0 0x0 0x0f121000 0x8000>; > + > + frame@0 { > + reg = <0x0 0x1000>, > + <0x1000 0x1000>; > + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; > + frame-number = <0>; > + }; > + > + frame@2000 { > + reg = <0x2000 0x1000>; > + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; > + frame-number = <1>; > + status = "disabled"; > + }; > + > + frame@3000 { > + reg = <0x3000 0x1000>; > + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; > + frame-number = <2>; > + status = "disabled"; > + }; > + > + frame@4000 { > + reg = <0x4000 0x1000>; > + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; > + frame-number = <3>; > + status = "disabled"; > + }; > + > + frame@5000 { > + reg = <0x5000 0x1000>; > + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; > + frame-number = <4>; > + status = "disabled"; > + }; > + > + frame@6000 { > + reg = <0x6000 0x1000>; > + interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; > + frame-number = <5>; > + status = "disabled"; > + }; > + > + frame@7000 { > + reg = <0x7000 0x1000>; > + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; > + frame-number = <6>; > + status = "disabled"; > + }; > + }; > + > + intc: interrupt-controller@f200000 { > + compatible = "arm,gic-v3"; > + reg = <0x0 0x0f200000 0x0 0x10000>, > + <0x0 0x0f300000 0x0 0x100000>; > + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; > + #interrupt-cells = <3>; > + interrupt-controller; > + interrupt-parent = <&intc>; > + #redistributor-regions = <1>; > + redistributor-stride = <0x0 0x20000>; > + }; > + > + cpufreq_hw: cpufreq@f521000 { > + compatible = "qcom,qcm2290-cpufreq-hw", "qcom,cpufreq-hw"; > + reg = <0x0 0x0f521000 0x0 0x1000>; > + reg-names = "freq-domain0"; > + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-names = "dcvsh-irq-0"; > + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GPLL0>; > + clock-names = "xo", "alternate"; > + > + #freq-domain-cells = <1>; > + #clock-cells = <1>; > + }; > + }; > + > + thermal-zones { > + mapss-thermal { > + polling-delay-passive = <0>; > + polling-delay = <0>; > + > + thermal-sensors = <&tsens0 0>; > + > + trips { > + mapss_alert0: trip-point0 { > + temperature = <90000>; > + hysteresis = <2000>; > + type = "passive"; > + }; > + > + mapss_alert1: trip-point1 { > + temperature = <95000>; > + hysteresis = <2000>; > + type = "passive"; > + }; > + > + mapss_crit: mapss-crit { > + temperature = <110000>; > + hysteresis = <1000>; > + type = "critical"; > + }; > + }; > + }; > + > + video-thermal { > + polling-delay-passive = <0>; > + polling-delay = <0>; > + > + thermal-sensors = <&tsens0 1>; > + > + trips { > + video_alert0: trip-point0 { > + temperature = <90000>; > + hysteresis = <2000>; > + type = "passive"; > + }; > + > + video_alert1: trip-point1 { > + temperature = <95000>; > + hysteresis = <2000>; > + type = "passive"; > + }; > + > + video_crit: video-crit { > + temperature = <110000>; > + hysteresis = <1000>; > + type = "critical"; > + }; > + }; > + }; > + > + wlan-thermal { > + polling-delay-passive = <0>; > + polling-delay = <0>; > + > + thermal-sensors = <&tsens0 2>; > + > + trips { > + wlan_alert0: trip-point0 { > + temperature = <90000>; > + hysteresis = <2000>; > + type = "passive"; > + }; > + > + wlan_alert1: trip-point1 { > + temperature = <95000>; > + hysteresis = <2000>; > + type = "passive"; > + }; > + > + wlan_crit: wlan-crit { > + temperature = <110000>; > + hysteresis = <1000>; > + type = "critical"; > + }; > + }; > + }; > + > + cpuss0-thermal { > + polling-delay-passive = <0>; > + polling-delay = <0>; > + > + thermal-sensors = <&tsens0 3>; > + > + trips { > + cpuss0_alert0: trip-point0 { > + temperature = <90000>; > + hysteresis = <2000>; > + type = "passive"; > + }; > + > + cpuss0_alert1: trip-point1 { > + temperature = <95000>; > + hysteresis = <2000>; > + type = "passive"; > + }; > + > + cpuss0_crit: cpuss0-crit { > + temperature = <110000>; > + hysteresis = <1000>; > + type = "critical"; > + }; > + }; > + }; > + > + cpuss1-thermal { > + polling-delay-passive = <0>; > + polling-delay = <0>; > + > + thermal-sensors = <&tsens0 4>; > + > + trips { > + cpuss1_alert0: trip-point0 { > + temperature = <90000>; > + hysteresis = <2000>; > + type = "passive"; > + }; > + > + cpuss1_alert1: trip-point1 { > + temperature = <95000>; > + hysteresis = <2000>; > + type = "passive"; > + }; > + > + cpuss1_crit: cpuss1-crit { > + temperature = <110000>; > + hysteresis = <1000>; > + type = "critical"; > + }; > + }; > + }; > + > + mdm0-thermal { > + polling-delay-passive = <0>; > + polling-delay = <0>; > + > + thermal-sensors = <&tsens0 5>; > + > + trips { > + mdm0_alert0: trip-point0 { > + temperature = <90000>; > + hysteresis = <2000>; > + type = "passive"; > + }; > + > + mdm0_alert1: trip-point1 { > + temperature = <95000>; > + hysteresis = <2000>; > + type = "passive"; > + }; > + > + mdm0_crit: mdm0-crit { > + temperature = <110000>; > + hysteresis = <1000>; > + type = "critical"; > + }; > + }; > + }; > + > + mdm1-thermal { > + polling-delay-passive = <0>; > + polling-delay = <0>; > + > + thermal-sensors = <&tsens0 6>; > + > + trips { > + mdm1_alert0: trip-point0 { > + temperature = <90000>; > + hysteresis = <2000>; > + type = "passive"; > + }; > + > + mdm1_alert1: trip-point1 { > + temperature = <95000>; > + hysteresis = <2000>; > + type = "passive"; > + }; > + > + mdm1_crit: mdm1-crit { > + temperature = <110000>; > + hysteresis = <1000>; > + type = "critical"; > + }; > + }; > + }; > + > + gpu-thermal { > + polling-delay-passive = <0>; > + polling-delay = <0>; > + > + thermal-sensors = <&tsens0 7>; > + > + trips { > + gpu_alert0: trip-point0 { > + temperature = <90000>; > + hysteresis = <2000>; > + type = "passive"; > + }; > + > + gpu_alert1: trip-point1 { > + temperature = <95000>; > + hysteresis = <2000>; > + type = "passive"; > + }; > + > + gpu_crit: gpu-crit { > + temperature = <110000>; > + hysteresis = <1000>; > + type = "critical"; > + }; > + }; > + }; > + > + hm-center-thermal { > + polling-delay-passive = <0>; > + polling-delay = <0>; > + > + thermal-sensors = <&tsens0 8>; > + > + trips { > + hm_center_alert0: trip-point0 { > + temperature = <90000>; > + hysteresis = <2000>; > + type = "passive"; > + }; > + > + hm_center_alert1: trip-point1 { > + temperature = <95000>; > + hysteresis = <2000>; > + type = "passive"; > + }; > + > + hm_center_crit: hm-center-crit { > + temperature = <110000>; > + hysteresis = <1000>; > + type = "critical"; > + }; > + }; > + }; > + > + camera-thermal { > + polling-delay-passive = <0>; > + polling-delay = <0>; > + > + thermal-sensors = <&tsens0 9>; > + > + trips { > + camera_alert0: trip-point0 { > + temperature = <90000>; > + hysteresis = <2000>; > + type = "passive"; > + }; > + > + camera_alert1: trip-point1 { > + temperature = <95000>; > + hysteresis = <2000>; > + type = "passive"; > + }; > + > + camera_crit: camera-crit { > + temperature = <110000>; > + hysteresis = <1000>; > + type = "critical"; > + }; > + }; > + }; > + }; > + > + timer { > + compatible = "arm,armv8-timer"; > + interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, > + <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, > + <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, > + <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; > + }; > +}; > > -- > 2.40.0 >
On 7.04.2023 20:35, Bjorn Andersson wrote: > On Wed, Apr 05, 2023 at 05:50:32PM +0200, Konrad Dybcio wrote: >> Add an initial device tree for the QCM2290 low-end SoC, featuring 4 >> "customized" Cortex-A53 cores and up to 4 GiB of LPDDR(3/4X). >> >> This revision brings support for: >> - TSENS & thermal zones >> - SDHCI1/2 >> - I2C, SPI, UART >> - MPSS >> - ADSP >> - Wi-Fi >> >> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> >> --- >> arch/arm64/boot/dts/qcom/Makefile | 1 + >> arch/arm64/boot/dts/qcom/qcm2290.dtsi | 1561 +++++++++++++++++++++++++++++++++ >> 2 files changed, 1562 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile >> index 1a29403400b7..6fc8d6664f0c 100644 >> --- a/arch/arm64/boot/dts/qcom/Makefile >> +++ b/arch/arm64/boot/dts/qcom/Makefile >> @@ -70,6 +70,7 @@ dtb-$(CONFIG_ARCH_QCOM) += msm8998-xiaomi-sagit.dtb >> dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-1000.dtb >> dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-4000.dtb >> dtb-$(CONFIG_ARCH_QCOM) += qdu1000-idp.dtb >> +dtb-$(CONFIG_ARCH_QCOM) += qrb2210-rb1.dtb > > I moved this to the patch that actually introduces rb1.dts Thanks for spotting this! Konrad > > Thanks, > Bjorn > >> dtb-$(CONFIG_ARCH_QCOM) += qrb5165-rb5.dtb >> dtb-$(CONFIG_ARCH_QCOM) += qrb5165-rb5-vision-mezzanine.dtb >> dtb-$(CONFIG_ARCH_QCOM) += qru1000-idp.dtb >> diff --git a/arch/arm64/boot/dts/qcom/qcm2290.dtsi b/arch/arm64/boot/dts/qcom/qcm2290.dtsi >> new file mode 100644 >> index 000000000000..ae5abc76bcc7 >> --- /dev/null >> +++ b/arch/arm64/boot/dts/qcom/qcm2290.dtsi >> @@ -0,0 +1,1561 @@ >> +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) >> +/* >> + * Copyright (c) 2023, Linaro Ltd >> + * >> + * Based on sm6115.dtsi and previous efforts by Shawn Guo & Loic Poulain. >> + */ >> + >> +#include <dt-bindings/clock/qcom,gcc-qcm2290.h> >> +#include <dt-bindings/clock/qcom,rpmcc.h> >> +#include <dt-bindings/dma/qcom-gpi.h> >> +#include <dt-bindings/firmware/qcom,scm.h> >> +#include <dt-bindings/gpio/gpio.h> >> +#include <dt-bindings/interrupt-controller/arm-gic.h> >> +#include <dt-bindings/power/qcom-rpmpd.h> >> + >> +/ { >> + interrupt-parent = <&intc>; >> + >> + #address-cells = <2>; >> + #size-cells = <2>; >> + >> + chosen { }; >> + >> + clocks { >> + xo_board: xo-board { >> + compatible = "fixed-clock"; >> + #clock-cells = <0>; >> + }; >> + >> + sleep_clk: sleep-clk { >> + compatible = "fixed-clock"; >> + clock-frequency = <32764>; >> + #clock-cells = <0>; >> + }; >> + }; >> + >> + cpus { >> + #address-cells = <2>; >> + #size-cells = <0>; >> + >> + CPU0: cpu@0 { >> + device_type = "cpu"; >> + compatible = "arm,cortex-a53"; >> + reg = <0x0 0x0>; >> + clocks = <&cpufreq_hw 0>; >> + capacity-dmips-mhz = <1024>; >> + dynamic-power-coefficient = <100>; >> + enable-method = "psci"; >> + next-level-cache = <&L2_0>; >> + qcom,freq-domain = <&cpufreq_hw 0>; >> + L2_0: l2-cache { >> + compatible = "cache"; >> + cache-level = <2>; >> + }; >> + }; >> + >> + CPU1: cpu@1 { >> + device_type = "cpu"; >> + compatible = "arm,cortex-a53"; >> + reg = <0x0 0x1>; >> + clocks = <&cpufreq_hw 0>; >> + capacity-dmips-mhz = <1024>; >> + dynamic-power-coefficient = <100>; >> + enable-method = "psci"; >> + next-level-cache = <&L2_0>; >> + qcom,freq-domain = <&cpufreq_hw 0>; >> + }; >> + >> + CPU2: cpu@2 { >> + device_type = "cpu"; >> + compatible = "arm,cortex-a53"; >> + reg = <0x0 0x2>; >> + clocks = <&cpufreq_hw 0>; >> + capacity-dmips-mhz = <1024>; >> + dynamic-power-coefficient = <100>; >> + enable-method = "psci"; >> + next-level-cache = <&L2_0>; >> + qcom,freq-domain = <&cpufreq_hw 0>; >> + }; >> + >> + CPU3: cpu@3 { >> + device_type = "cpu"; >> + compatible = "arm,cortex-a53"; >> + reg = <0x0 0x3>; >> + clocks = <&cpufreq_hw 0>; >> + capacity-dmips-mhz = <1024>; >> + dynamic-power-coefficient = <100>; >> + enable-method = "psci"; >> + next-level-cache = <&L2_0>; >> + qcom,freq-domain = <&cpufreq_hw 0>; >> + }; >> + >> + cpu-map { >> + cluster0 { >> + core0 { >> + cpu = <&CPU0>; >> + }; >> + >> + core1 { >> + cpu = <&CPU1>; >> + }; >> + >> + core2 { >> + cpu = <&CPU2>; >> + }; >> + >> + core3 { >> + cpu = <&CPU3>; >> + }; >> + }; >> + }; >> + }; >> + >> + firmware { >> + scm: scm { >> + compatible = "qcom,scm-qcm2290", "qcom,scm"; >> + clocks = <&rpmcc RPM_SMD_CE1_CLK>; >> + clock-names = "core"; >> + #reset-cells = <1>; >> + }; >> + }; >> + >> + memory@40000000 { >> + device_type = "memory"; >> + /* We expect the bootloader to fill in the size */ >> + reg = <0 0x40000000 0 0>; >> + }; >> + >> + pmu { >> + compatible = "arm,armv8-pmuv3"; >> + interrupts = <GIC_PPI 6 IRQ_TYPE_LEVEL_HIGH>; >> + }; >> + >> + psci { >> + compatible = "arm,psci-1.0"; >> + method = "smc"; >> + }; >> + >> + reserved_memory: reserved-memory { >> + #address-cells = <2>; >> + #size-cells = <2>; >> + ranges; >> + >> + hyp_mem: hyp@45700000 { >> + reg = <0x0 0x45700000 0x0 0x600000>; >> + no-map; >> + }; >> + >> + xbl_aop_mem: xbl-aop@45e00000 { >> + reg = <0x0 0x45e00000 0x0 0x140000>; >> + no-map; >> + }; >> + >> + sec_apps_mem: sec-apps@45fff000 { >> + reg = <0x0 0x45fff000 0x0 0x1000>; >> + no-map; >> + }; >> + >> + smem_mem: smem@46000000 { >> + compatible = "qcom,smem"; >> + reg = <0x0 0x46000000 0x0 0x200000>; >> + no-map; >> + >> + hwlocks = <&tcsr_mutex 3>; >> + qcom,rpm-msg-ram = <&rpm_msg_ram>; >> + }; >> + >> + pil_modem_mem: modem@4ab00000 { >> + reg = <0x0 0x4ab00000 0x0 0x6900000>; >> + no-map; >> + }; >> + >> + pil_video_mem: video@51400000 { >> + reg = <0x0 0x51400000 0x0 0x500000>; >> + no-map; >> + }; >> + >> + wlan_msa_mem: wlan-msa@51900000 { >> + reg = <0x0 0x51900000 0x0 0x100000>; >> + no-map; >> + }; >> + >> + pil_adsp_mem: adsp@51a00000 { >> + reg = <0x0 0x51a00000 0x0 0x1c00000>; >> + no-map; >> + }; >> + >> + pil_ipa_fw_mem: ipa-fw@53600000 { >> + reg = <0x0 0x53600000 0x0 0x10000>; >> + no-map; >> + }; >> + >> + pil_ipa_gsi_mem: ipa-gsi@53610000 { >> + reg = <0x0 0x53610000 0x0 0x5000>; >> + no-map; >> + }; >> + >> + pil_gpu_mem: zap@53615000 { >> + compatible = "shared-dma-pool"; >> + reg = <0x0 0x53615000 0x0 0x2000>; >> + no-map; >> + }; >> + >> + cont_splash_memory: framebuffer@5c000000 { >> + reg = <0x0 0x5c000000 0x0 0x00f00000>; >> + no-map; >> + }; >> + >> + dfps_data_memory: dpfs-data@5cf00000 { >> + reg = <0x0 0x5cf00000 0x0 0x0100000>; >> + no-map; >> + }; >> + >> + removed_mem: reserved@60000000 { >> + reg = <0x0 0x60000000 0x0 0x3900000>; >> + no-map; >> + }; >> + >> + rmtfs_mem: memory@89b01000 { >> + compatible = "qcom,rmtfs-mem"; >> + reg = <0x0 0x89b01000 0x0 0x200000>; >> + no-map; >> + >> + qcom,client-id = <1>; >> + qcom,vmid = <QCOM_SCM_VMID_MSS_MSA QCOM_SCM_VMID_NAV>; >> + }; >> + }; >> + >> + rpm-glink { >> + compatible = "qcom,glink-rpm"; >> + interrupts = <GIC_SPI 194 IRQ_TYPE_EDGE_RISING>; >> + qcom,rpm-msg-ram = <&rpm_msg_ram>; >> + mboxes = <&apcs_glb 0>; >> + >> + rpm_requests: rpm-requests { >> + compatible = "qcom,rpm-qcm2290"; >> + qcom,glink-channels = "rpm_requests"; >> + >> + rpmcc: clock-controller { >> + compatible = "qcom,rpmcc-qcm2290", "qcom,rpmcc"; >> + clocks = <&xo_board>; >> + clock-names = "xo"; >> + #clock-cells = <1>; >> + }; >> + >> + rpmpd: power-controller { >> + compatible = "qcom,qcm2290-rpmpd"; >> + #power-domain-cells = <1>; >> + operating-points-v2 = <&rpmpd_opp_table>; >> + >> + rpmpd_opp_table: opp-table { >> + compatible = "operating-points-v2"; >> + >> + rpmpd_opp_min_svs: opp1 { >> + opp-level = <RPM_SMD_LEVEL_MIN_SVS>; >> + }; >> + >> + rpmpd_opp_low_svs: opp2 { >> + opp-level = <RPM_SMD_LEVEL_LOW_SVS>; >> + }; >> + >> + rpmpd_opp_svs: opp3 { >> + opp-level = <RPM_SMD_LEVEL_SVS>; >> + }; >> + >> + rpmpd_opp_svs_plus: opp4 { >> + opp-level = <RPM_SMD_LEVEL_SVS_PLUS>; >> + }; >> + >> + rpmpd_opp_nom: opp5 { >> + opp-level = <RPM_SMD_LEVEL_NOM>; >> + }; >> + >> + rpmpd_opp_nom_plus: opp6 { >> + opp-level = <RPM_SMD_LEVEL_NOM_PLUS>; >> + }; >> + >> + rpmpd_opp_turbo: opp7 { >> + opp-level = <RPM_SMD_LEVEL_TURBO>; >> + }; >> + >> + rpmpd_opp_turbo_plus: opp8 { >> + opp-level = <RPM_SMD_LEVEL_TURBO_NO_CPR>; >> + }; >> + }; >> + }; >> + }; >> + }; >> + >> + smp2p-adsp { >> + compatible = "qcom,smp2p"; >> + qcom,smem = <443>, <429>; >> + >> + interrupts = <GIC_SPI 279 IRQ_TYPE_EDGE_RISING>; >> + >> + mboxes = <&apcs_glb 10>; >> + >> + qcom,local-pid = <0>; >> + qcom,remote-pid = <2>; >> + >> + adsp_smp2p_out: master-kernel { >> + qcom,entry-name = "master-kernel"; >> + #qcom,smem-state-cells = <1>; >> + }; >> + >> + adsp_smp2p_in: slave-kernel { >> + qcom,entry-name = "slave-kernel"; >> + interrupt-controller; >> + #interrupt-cells = <2>; >> + }; >> + }; >> + >> + smp2p-mpss { >> + compatible = "qcom,smp2p"; >> + qcom,smem = <435>, <428>; >> + >> + interrupts = <GIC_SPI 70 IRQ_TYPE_EDGE_RISING>; >> + >> + mboxes = <&apcs_glb 14>; >> + >> + qcom,local-pid = <0>; >> + qcom,remote-pid = <1>; >> + >> + modem_smp2p_out: master-kernel { >> + qcom,entry-name = "master-kernel"; >> + #qcom,smem-state-cells = <1>; >> + }; >> + >> + modem_smp2p_in: slave-kernel { >> + qcom,entry-name = "slave-kernel"; >> + interrupt-controller; >> + #interrupt-cells = <2>; >> + }; >> + >> + wlan_smp2p_in: wlan-wpss-to-ap { >> + qcom,entry-name = "wlan"; >> + interrupt-controller; >> + #interrupt-cells = <2>; >> + }; >> + }; >> + >> + soc: soc@0 { >> + compatible = "simple-bus"; >> + #address-cells = <2>; >> + #size-cells = <2>; >> + ranges = <0 0 0 0 0x10 0>; >> + dma-ranges = <0 0 0 0 0x10 0>; >> + >> + tcsr_mutex: hwlock@340000 { >> + compatible = "qcom,tcsr-mutex"; >> + reg = <0x0 0x00340000 0x0 0x20000>; >> + #hwlock-cells = <1>; >> + }; >> + >> + tlmm: pinctrl@500000 { >> + compatible = "qcom,qcm2290-tlmm"; >> + reg = <0x0 0x00500000 0x0 0x300000>; >> + interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; >> + gpio-controller; >> + gpio-ranges = <&tlmm 0 0 127>; >> + #gpio-cells = <2>; >> + interrupt-controller; >> + #interrupt-cells = <2>; >> + >> + qup_i2c0_default: qup-i2c0-default-state { >> + pins = "gpio0", "gpio1"; >> + function = "qup0"; >> + drive-strength = <2>; >> + bias-pull-up; >> + }; >> + >> + qup_i2c1_default: qup-i2c1-default-state { >> + pins = "gpio4", "gpio5"; >> + function = "qup1"; >> + drive-strength = <2>; >> + bias-pull-up; >> + }; >> + >> + qup_i2c2_default: qup-i2c2-default-state { >> + pins = "gpio6", "gpio7"; >> + function = "qup2"; >> + drive-strength = <2>; >> + bias-pull-up; >> + }; >> + >> + qup_i2c3_default: qup-i2c3-default-state { >> + pins = "gpio8", "gpio9"; >> + function = "qup3"; >> + drive-strength = <2>; >> + bias-pull-up; >> + }; >> + >> + qup_i2c4_default: qup-i2c4-default-state { >> + pins = "gpio12", "gpio13"; >> + function = "qup4"; >> + drive-strength = <2>; >> + bias-pull-up; >> + }; >> + >> + qup_i2c5_default: qup-i2c5-default-state { >> + pins = "gpio14", "gpio15"; >> + function = "qup5"; >> + drive-strength = <2>; >> + bias-pull-up; >> + }; >> + >> + qup_spi0_default: qup-spi0-default-state { >> + pins = "gpio0", "gpio1","gpio2", "gpio3"; >> + function = "qup0"; >> + drive-strength = <2>; >> + bias-pull-up; >> + }; >> + >> + qup_spi1_default: qup-spi1-default-state { >> + pins = "gpio4", "gpio5", "gpio69", "gpio70"; >> + function = "qup1"; >> + drive-strength = <2>; >> + bias-pull-up; >> + }; >> + >> + qup_spi2_default: qup-spi2-default-state { >> + pins = "gpio6", "gpio7", "gpio71", "gpio80"; >> + function = "qup2"; >> + drive-strength = <2>; >> + bias-pull-up; >> + }; >> + >> + qup_spi3_default: qup-spi3-default-state { >> + pins = "gpio8", "gpio9", "gpio10", "gpio11"; >> + function = "qup3"; >> + drive-strength = <2>; >> + bias-pull-up; >> + }; >> + >> + qup_spi4_default: qup-spi4-default-state { >> + pins = "gpio12", "gpio13", "gpio96", "gpio97"; >> + function = "qup4"; >> + drive-strength = <2>; >> + bias-pull-up; >> + }; >> + >> + qup_spi5_default: qup-spi5-default-state { >> + pins = "gpio14", "gpio15", "gpio16", "gpio17"; >> + function = "qup5"; >> + drive-strength = <2>; >> + bias-pull-up; >> + }; >> + >> + qup_uart0_default: qup-uart0-default-state { >> + pins = "gpio0", "gpio1", "gpio2", "gpio3"; >> + function = "qup0"; >> + drive-strength = <2>; >> + bias-disable; >> + }; >> + >> + qup_uart4_default: qup-uart4-default-state { >> + pins = "gpio12", "gpio13"; >> + function = "qup4"; >> + drive-strength = <2>; >> + bias-disable; >> + }; >> + >> + sdc1_state_on: sdc1-on-state { >> + clk-pins { >> + pins = "sdc1_clk"; >> + drive-strength = <16>; >> + bias-disable; >> + }; >> + >> + cmd-pins { >> + pins = "sdc1_cmd"; >> + drive-strength = <10>; >> + bias-pull-up; >> + }; >> + >> + data-pins { >> + pins = "sdc1_data"; >> + drive-strength = <10>; >> + bias-pull-up; >> + }; >> + >> + rclk-pins { >> + pins = "sdc1_rclk"; >> + bias-pull-down; >> + }; >> + }; >> + >> + sdc1_state_off: sdc1-off-state { >> + clk-pins { >> + pins = "sdc1_clk"; >> + drive-strength = <2>; >> + bias-disable; >> + }; >> + >> + cmd-pins { >> + pins = "sdc1_cmd"; >> + drive-strength = <2>; >> + bias-pull-up; >> + }; >> + >> + data-pins { >> + pins = "sdc1_data"; >> + drive-strength = <2>; >> + bias-pull-up; >> + }; >> + >> + rclk-pins { >> + pins = "sdc1_rclk"; >> + bias-pull-down; >> + }; >> + }; >> + >> + sdc2_state_on: sdc2-on-state { >> + clk-pins { >> + pins = "sdc2_clk"; >> + drive-strength = <16>; >> + bias-disable; >> + }; >> + >> + cmd-pins { >> + pins = "sdc2_cmd"; >> + drive-strength = <10>; >> + bias-pull-up; >> + }; >> + >> + data-pins { >> + pins = "sdc2_data"; >> + drive-strength = <10>; >> + bias-pull-up; >> + }; >> + }; >> + >> + sdc2_state_off: sdc2-off-state { >> + clk-pins { >> + pins = "sdc2_clk"; >> + drive-strength = <2>; >> + bias-disable; >> + }; >> + >> + cmd-pins { >> + pins = "sdc2_cmd"; >> + drive-strength = <2>; >> + bias-pull-up; >> + }; >> + >> + data-pins { >> + pins = "sdc2_data"; >> + drive-strength = <2>; >> + bias-pull-up; >> + }; >> + }; >> + }; >> + >> + gcc: clock-controller@1400000 { >> + compatible = "qcom,gcc-qcm2290"; >> + reg = <0x0 0x01400000 0x0 0x1f0000>; >> + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&sleep_clk>; >> + clock-names = "bi_tcxo", "sleep_clk"; >> + #clock-cells = <1>; >> + #reset-cells = <1>; >> + #power-domain-cells = <1>; >> + }; >> + >> + usb_hsphy: phy@1613000 { >> + compatible = "qcom,qcm2290-qusb2-phy"; >> + reg = <0x0 0x01613000 0x0 0x180>; >> + >> + clocks = <&gcc GCC_AHB2PHY_USB_CLK>, >> + <&rpmcc RPM_SMD_XO_CLK_SRC>; >> + clock-names = "cfg_ahb", "ref"; >> + >> + resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; >> + nvmem-cells = <&qusb2_hstx_trim>; >> + #phy-cells = <0>; >> + >> + status = "disabled"; >> + }; >> + >> + qfprom@1b44000 { >> + compatible = "qcom,qcm2290-qfprom", "qcom,qfprom"; >> + reg = <0x0 0x01b44000 0x0 0x3000>; >> + #address-cells = <1>; >> + #size-cells = <1>; >> + >> + qusb2_hstx_trim: hstx-trim@25b { >> + reg = <0x25b 0x1>; >> + bits = <1 4>; >> + }; >> + }; >> + >> + spmi_bus: spmi@1c40000 { >> + compatible = "qcom,spmi-pmic-arb"; >> + reg = <0x0 0x01c40000 0x0 0x1100>, >> + <0x0 0x01e00000 0x0 0x2000000>, >> + <0x0 0x03e00000 0x0 0x100000>, >> + <0x0 0x03f00000 0x0 0xa0000>, >> + <0x0 0x01c0a000 0x0 0x26000>; >> + reg-names = "core", >> + "chnls", >> + "obsrvr", >> + "intr", >> + "cnfg"; >> + interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; >> + interrupt-names = "periph_irq"; >> + qcom,ee = <0>; >> + qcom,channel = <0>; >> + #address-cells = <2>; >> + #size-cells = <0>; >> + interrupt-controller; >> + #interrupt-cells = <4>; >> + }; >> + >> + tsens0: thermal-sensor@4411000 { >> + compatible = "qcom,qcm2290-tsens", "qcom,tsens-v2"; >> + reg = <0x0 0x04411000 0x0 0x1ff>, >> + <0x0 0x04410000 0x0 0x8>; >> + #qcom,sensors = <10>; >> + interrupts = <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; >> + interrupt-names = "uplow", "critical"; >> + #thermal-sensor-cells = <1>; >> + }; >> + >> + rng: rng@4453000 { >> + compatible = "qcom,prng-ee"; >> + reg = <0x0 0x04453000 0x0 0x1000>; >> + clocks = <&rpmcc RPM_SMD_HWKM_CLK>; >> + clock-names = "core"; >> + }; >> + >> + rpm_msg_ram: sram@45f0000 { >> + compatible = "qcom,rpm-msg-ram"; >> + reg = <0x0 0x045f0000 0x0 0x7000>; >> + }; >> + >> + sram@4690000 { >> + compatible = "qcom,rpm-stats"; >> + reg = <0x0 0x04690000 0x0 0x10000>; >> + }; >> + >> + sdhc_1: mmc@4744000 { >> + compatible = "qcom,qcm2290-sdhci", "qcom,sdhci-msm-v5"; >> + reg = <0x0 0x04744000 0x0 0x1000>, >> + <0x0 0x04745000 0x0 0x1000>, >> + <0x0 0x04748000 0x0 0x8000>; >> + reg-names = "hc", >> + "cqhci", >> + "ice"; >> + >> + interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; >> + interrupt-names = "hc_irq", "pwr_irq"; >> + >> + clocks = <&gcc GCC_SDCC1_AHB_CLK>, >> + <&gcc GCC_SDCC1_APPS_CLK>, >> + <&rpmcc RPM_SMD_XO_CLK_SRC>, >> + <&gcc GCC_SDCC1_ICE_CORE_CLK>; >> + clock-names = "iface", >> + "core", >> + "xo", >> + "ice"; >> + >> + resets = <&gcc GCC_SDCC1_BCR>; >> + >> + power-domains = <&rpmpd QCM2290_VDDCX>; >> + iommus = <&apps_smmu 0xc0 0x0>; >> + >> + qcom,dll-config = <0x000f642c>; >> + qcom,ddr-config = <0x80040868>; >> + bus-width = <8>; >> + >> + status = "disabled"; >> + }; >> + >> + sdhc_2: mmc@4784000 { >> + compatible = "qcom,qcm2290-sdhci", "qcom,sdhci-msm-v5"; >> + reg = <0x0 0x04784000 0x0 0x1000>; >> + reg-names = "hc"; >> + >> + interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; >> + interrupt-names = "hc_irq", "pwr_irq"; >> + >> + clocks = <&gcc GCC_SDCC2_AHB_CLK>, >> + <&gcc GCC_SDCC2_APPS_CLK>, >> + <&rpmcc RPM_SMD_XO_CLK_SRC>; >> + clock-names = "iface", >> + "core", >> + "xo"; >> + >> + resets = <&gcc GCC_SDCC2_BCR>; >> + >> + power-domains = <&rpmpd QCM2290_VDDCX>; >> + operating-points-v2 = <&sdhc2_opp_table>; >> + iommus = <&apps_smmu 0xa0 0x0>; >> + >> + qcom,dll-config = <0x0007642c>; >> + qcom,ddr-config = <0x80040868>; >> + bus-width = <4>; >> + >> + status = "disabled"; >> + >> + sdhc2_opp_table: opp-table { >> + compatible = "operating-points-v2"; >> + >> + opp-100000000 { >> + opp-hz = /bits/ 64 <100000000>; >> + required-opps = <&rpmpd_opp_low_svs>; >> + }; >> + >> + opp-202000000 { >> + opp-hz = /bits/ 64 <202000000>; >> + required-opps = <&rpmpd_opp_svs_plus>; >> + }; >> + }; >> + }; >> + >> + gpi_dma0: dma-controller@4a00000 { >> + compatible = "qcom,qcm2290-gpi-dma", "qcom,sm6350-gpi-dma"; >> + reg = <0x0 0x04a00000 0x0 0x60000>; >> + interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>; >> + dma-channels = <10>; >> + dma-channel-mask = <0x1f>; >> + iommus = <&apps_smmu 0xf6 0x0>; >> + #dma-cells = <3>; >> + status = "disabled"; >> + }; >> + >> + qupv3_id_0: geniqup@4ac0000 { >> + compatible = "qcom,geni-se-qup"; >> + reg = <0x0 0x04ac0000 0x0 0x2000>; >> + clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, >> + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; >> + clock-names = "m-ahb", "s-ahb"; >> + iommus = <&apps_smmu 0xe3 0x0>; >> + #address-cells = <2>; >> + #size-cells = <2>; >> + ranges; >> + status = "disabled"; >> + >> + i2c0: i2c@4a80000 { >> + compatible = "qcom,geni-i2c"; >> + reg = <0x0 0x04a80000 0x0 0x4000>; >> + interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>; >> + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; >> + clock-names = "se"; >> + pinctrl-0 = <&qup_i2c0_default>; >> + pinctrl-names = "default"; >> + dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, >> + <&gpi_dma0 1 0 QCOM_GPI_I2C>; >> + dma-names = "tx", "rx"; >> + #address-cells = <1>; >> + #size-cells = <0>; >> + status = "disabled"; >> + }; >> + >> + spi0: spi@4a80000 { >> + compatible = "qcom,geni-spi"; >> + reg = <0x0 0x04a80000 0x0 0x4000>; >> + interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>; >> + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; >> + clock-names = "se"; >> + pinctrl-0 = <&qup_spi0_default>; >> + pinctrl-names = "default"; >> + dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, >> + <&gpi_dma0 1 0 QCOM_GPI_SPI>; >> + dma-names = "tx", "rx"; >> + #address-cells = <1>; >> + #size-cells = <0>; >> + status = "disabled"; >> + }; >> + >> + uart0: serial@4a80000 { >> + compatible = "qcom,geni-uart"; >> + reg = <0x0 0x04a80000 0x0 0x4000>; >> + interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>; >> + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; >> + clock-names = "se"; >> + pinctrl-0 = <&qup_uart0_default>; >> + pinctrl-names = "default"; >> + status = "disabled"; >> + }; >> + >> + i2c1: i2c@4a84000 { >> + compatible = "qcom,geni-i2c"; >> + reg = <0x0 0x04a84000 0x0 0x4000>; >> + interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>; >> + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; >> + clock-names = "se"; >> + pinctrl-0 = <&qup_i2c1_default>; >> + pinctrl-names = "default"; >> + dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, >> + <&gpi_dma0 1 1 QCOM_GPI_I2C>; >> + dma-names = "tx", "rx"; >> + #address-cells = <1>; >> + #size-cells = <0>; >> + status = "disabled"; >> + }; >> + >> + spi1: spi@4a84000 { >> + compatible = "qcom,geni-spi"; >> + reg = <0x0 0x04a84000 0x0 0x4000>; >> + interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>; >> + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; >> + clock-names = "se"; >> + pinctrl-0 = <&qup_spi1_default>; >> + pinctrl-names = "default"; >> + dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, >> + <&gpi_dma0 1 1 QCOM_GPI_SPI>; >> + dma-names = "tx", "rx"; >> + #address-cells = <1>; >> + #size-cells = <0>; >> + status = "disabled"; >> + }; >> + >> + i2c2: i2c@4a88000 { >> + compatible = "qcom,geni-i2c"; >> + reg = <0x0 0x04a88000 0x0 0x4000>; >> + interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>; >> + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; >> + clock-names = "se"; >> + pinctrl-0 = <&qup_i2c2_default>; >> + pinctrl-names = "default"; >> + dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, >> + <&gpi_dma0 1 2 QCOM_GPI_I2C>; >> + dma-names = "tx", "rx"; >> + #address-cells = <1>; >> + #size-cells = <0>; >> + status = "disabled"; >> + }; >> + >> + spi2: spi@4a88000 { >> + compatible = "qcom,geni-spi"; >> + reg = <0x0 0x04a88000 0x0 0x4000>; >> + interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>; >> + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; >> + clock-names = "se"; >> + pinctrl-0 = <&qup_spi2_default>; >> + pinctrl-names = "default"; >> + dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, >> + <&gpi_dma0 1 2 QCOM_GPI_SPI>; >> + dma-names = "tx", "rx"; >> + #address-cells = <1>; >> + #size-cells = <0>; >> + status = "disabled"; >> + }; >> + >> + i2c3: i2c@4a8c000 { >> + compatible = "qcom,geni-i2c"; >> + reg = <0x0 0x04a8c000 0x0 0x4000>; >> + interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>; >> + clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; >> + clock-names = "se"; >> + pinctrl-0 = <&qup_i2c3_default>; >> + pinctrl-names = "default"; >> + dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, >> + <&gpi_dma0 1 3 QCOM_GPI_I2C>; >> + dma-names = "tx", "rx"; >> + #address-cells = <1>; >> + #size-cells = <0>; >> + status = "disabled"; >> + }; >> + >> + spi3: spi@4a8c000 { >> + compatible = "qcom,geni-spi"; >> + reg = <0x0 0x04a8c000 0x0 0x4000>; >> + interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>; >> + clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; >> + clock-names = "se"; >> + pinctrl-0 = <&qup_spi3_default>; >> + pinctrl-names = "default"; >> + dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, >> + <&gpi_dma0 1 3 QCOM_GPI_SPI>; >> + dma-names = "tx", "rx"; >> + #address-cells = <1>; >> + #size-cells = <0>; >> + status = "disabled"; >> + }; >> + >> + i2c4: i2c@4a90000 { >> + compatible = "qcom,geni-i2c"; >> + reg = <0x0 0x04a90000 0x0 0x4000>; >> + interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>; >> + clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; >> + clock-names = "se"; >> + pinctrl-0 = <&qup_i2c4_default>; >> + pinctrl-names = "default"; >> + dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, >> + <&gpi_dma0 1 4 QCOM_GPI_I2C>; >> + dma-names = "tx", "rx"; >> + #address-cells = <1>; >> + #size-cells = <0>; >> + status = "disabled"; >> + }; >> + >> + spi4: spi@4a90000 { >> + compatible = "qcom,geni-spi"; >> + reg = <0x0 0x04a90000 0x0 0x4000>; >> + interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>; >> + clock-names = "se"; >> + clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; >> + pinctrl-names = "default"; >> + pinctrl-0 = <&qup_spi4_default>; >> + dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, >> + <&gpi_dma0 1 4 QCOM_GPI_SPI>; >> + dma-names = "tx", "rx"; >> + #address-cells = <1>; >> + #size-cells = <0>; >> + status = "disabled"; >> + }; >> + >> + uart4: serial@4a90000 { >> + compatible = "qcom,geni-uart"; >> + reg = <0x0 0x04a90000 0x0 0x4000>; >> + interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>; >> + clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; >> + clock-names = "se"; >> + pinctrl-0 = <&qup_uart4_default>; >> + pinctrl-names = "default"; >> + status = "disabled"; >> + }; >> + >> + i2c5: i2c@4a94000 { >> + compatible = "qcom,geni-i2c"; >> + reg = <0x0 0x04a94000 0x0 0x4000>; >> + interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>; >> + clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; >> + clock-names = "se"; >> + pinctrl-0 = <&qup_i2c5_default>; >> + pinctrl-names = "default"; >> + dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, >> + <&gpi_dma0 1 5 QCOM_GPI_I2C>; >> + dma-names = "tx", "rx"; >> + #address-cells = <1>; >> + #size-cells = <0>; >> + status = "disabled"; >> + }; >> + >> + spi5: spi@4a94000 { >> + compatible = "qcom,geni-spi"; >> + reg = <0x0 0x04a94000 0x0 0x4000>; >> + interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>; >> + clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; >> + clock-names = "se"; >> + pinctrl-0 = <&qup_spi5_default>; >> + pinctrl-names = "default"; >> + dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, >> + <&gpi_dma0 1 5 QCOM_GPI_SPI>; >> + dma-names = "tx", "rx"; >> + #address-cells = <1>; >> + #size-cells = <0>; >> + status = "disabled"; >> + }; >> + }; >> + >> + usb: usb@4ef8800 { >> + compatible = "qcom,qcm2290-dwc3", "qcom,dwc3"; >> + reg = <0x0 0x04ef8800 0x0 0x400>; >> + interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>; >> + interrupt-names = "hs_phy_irq", "ss_phy_irq"; >> + >> + clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, >> + <&gcc GCC_USB30_PRIM_MASTER_CLK>, >> + <&gcc GCC_SYS_NOC_USB3_PRIM_AXI_CLK>, >> + <&gcc GCC_USB30_PRIM_SLEEP_CLK>, >> + <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, >> + <&gcc GCC_USB3_PRIM_CLKREF_CLK>; >> + clock-names = "cfg_noc", >> + "core", >> + "iface", >> + "sleep", >> + "mock_utmi", >> + "xo"; >> + >> + assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, >> + <&gcc GCC_USB30_PRIM_MASTER_CLK>; >> + assigned-clock-rates = <19200000>, <133333333>; >> + >> + resets = <&gcc GCC_USB30_PRIM_BCR>; >> + power-domains = <&gcc GCC_USB30_PRIM_GDSC>; >> + wakeup-source; >> + >> + #address-cells = <2>; >> + #size-cells = <2>; >> + ranges; >> + >> + status = "disabled"; >> + >> + usb_dwc3: usb@4e00000 { >> + compatible = "snps,dwc3"; >> + reg = <0x0 0x04e00000 0x0 0xcd00>; >> + interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; >> + phys = <&usb_hsphy>; >> + phy-names = "usb2-phy"; >> + iommus = <&apps_smmu 0x120 0x0>; >> + snps,dis_u2_susphy_quirk; >> + snps,dis_enblslpm_quirk; >> + snps,has-lpm-erratum; >> + snps,hird-threshold = /bits/ 8 <0x10>; >> + snps,usb3_lpm_capable; >> + maximum-speed = "super-speed"; >> + dr_mode = "otg"; >> + }; >> + }; >> + >> + remoteproc_mpss: remoteproc@6080000 { >> + compatible = "qcom,qcm2290-mpss-pas", "qcom,sm6115-mpss-pas"; >> + reg = <0x0 0x06080000 0x0 0x100>; >> + >> + interrupts-extended = <&intc GIC_SPI 307 IRQ_TYPE_EDGE_RISING>, >> + <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, >> + <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, >> + <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, >> + <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, >> + <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; >> + interrupt-names = "wdog", >> + "fatal", >> + "ready", >> + "handover", >> + "stop-ack", >> + "shutdown-ack"; >> + >> + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; >> + clock-names = "xo"; >> + >> + power-domains = <&rpmpd QCM2290_VDDCX>; >> + >> + memory-region = <&pil_modem_mem>; >> + >> + qcom,smem-states = <&modem_smp2p_out 0>; >> + qcom,smem-state-names = "stop"; >> + >> + status = "disabled"; >> + >> + glink-edge { >> + interrupts = <GIC_SPI 68 IRQ_TYPE_EDGE_RISING>; >> + label = "mpss"; >> + qcom,remote-pid = <1>; >> + mboxes = <&apcs_glb 12>; >> + }; >> + }; >> + >> + remoteproc_adsp: remoteproc@ab00000 { >> + compatible = "qcom,qcm2290-adsp-pas", "qcom,sm6115-adsp-pas"; >> + reg = <0x0 0x0ab00000 0x0 0x100>; >> + >> + interrupts-extended = <&intc GIC_SPI 282 IRQ_TYPE_EDGE_RISING>, >> + <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, >> + <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, >> + <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, >> + <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; >> + interrupt-names = "wdog", >> + "fatal", >> + "ready", >> + "handover", >> + "stop-ack"; >> + >> + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; >> + clock-names = "xo"; >> + >> + power-domains = <&rpmpd QCM2290_VDD_LPI_CX>, >> + <&rpmpd QCM2290_VDD_LPI_MX>; >> + >> + memory-region = <&pil_adsp_mem>; >> + >> + qcom,smem-states = <&adsp_smp2p_out 0>; >> + qcom,smem-state-names = "stop"; >> + >> + status = "disabled"; >> + >> + glink-edge { >> + interrupts = <GIC_SPI 277 IRQ_TYPE_EDGE_RISING>; >> + label = "lpass"; >> + qcom,remote-pid = <2>; >> + mboxes = <&apcs_glb 8>; >> + }; >> + }; >> + >> + apps_smmu: iommu@c600000 { >> + compatible = "qcom,qcm2290-smmu-500", "qcom,smmu-500", "arm,mmu-500"; >> + reg = <0x0 0x0c600000 0x0 0x80000>; >> + #iommu-cells = <2>; >> + #global-interrupts = <1>; >> + >> + interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; >> + }; >> + >> + wifi: wifi@c800000 { >> + compatible = "qcom,wcn3990-wifi"; >> + reg = <0x0 0x0c800000 0x0 0x800000>; >> + reg-names = "membase"; >> + memory-region = <&wlan_msa_mem>; >> + interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; >> + iommus = <&apps_smmu 0x1a0 0x1>; >> + qcom,msa-fixed-perm; >> + status = "disabled"; >> + }; >> + >> + watchdog@f017000 { >> + compatible = "qcom,apss-wdt-qcm2290", "qcom,kpss-wdt"; >> + reg = <0x0 0x0f017000 0x0 0x1000>; >> + interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>, >> + <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; >> + clocks = <&sleep_clk>; >> + }; >> + >> + apcs_glb: mailbox@f111000 { >> + compatible = "qcom,qcm2290-apcs-hmss-global"; >> + reg = <0x0 0x0f111000 0x0 0x1000>; >> + #mbox-cells = <1>; >> + }; >> + >> + timer@f120000 { >> + compatible = "arm,armv7-timer-mem"; >> + reg = <0x0 0x0f120000 0x0 0x1000>; >> + #address-cells = <1>; >> + #size-cells = <1>; >> + ranges = <0 0x0 0x0f121000 0x8000>; >> + >> + frame@0 { >> + reg = <0x0 0x1000>, >> + <0x1000 0x1000>; >> + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; >> + frame-number = <0>; >> + }; >> + >> + frame@2000 { >> + reg = <0x2000 0x1000>; >> + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; >> + frame-number = <1>; >> + status = "disabled"; >> + }; >> + >> + frame@3000 { >> + reg = <0x3000 0x1000>; >> + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; >> + frame-number = <2>; >> + status = "disabled"; >> + }; >> + >> + frame@4000 { >> + reg = <0x4000 0x1000>; >> + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; >> + frame-number = <3>; >> + status = "disabled"; >> + }; >> + >> + frame@5000 { >> + reg = <0x5000 0x1000>; >> + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; >> + frame-number = <4>; >> + status = "disabled"; >> + }; >> + >> + frame@6000 { >> + reg = <0x6000 0x1000>; >> + interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; >> + frame-number = <5>; >> + status = "disabled"; >> + }; >> + >> + frame@7000 { >> + reg = <0x7000 0x1000>; >> + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; >> + frame-number = <6>; >> + status = "disabled"; >> + }; >> + }; >> + >> + intc: interrupt-controller@f200000 { >> + compatible = "arm,gic-v3"; >> + reg = <0x0 0x0f200000 0x0 0x10000>, >> + <0x0 0x0f300000 0x0 0x100000>; >> + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; >> + #interrupt-cells = <3>; >> + interrupt-controller; >> + interrupt-parent = <&intc>; >> + #redistributor-regions = <1>; >> + redistributor-stride = <0x0 0x20000>; >> + }; >> + >> + cpufreq_hw: cpufreq@f521000 { >> + compatible = "qcom,qcm2290-cpufreq-hw", "qcom,cpufreq-hw"; >> + reg = <0x0 0x0f521000 0x0 0x1000>; >> + reg-names = "freq-domain0"; >> + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; >> + interrupt-names = "dcvsh-irq-0"; >> + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GPLL0>; >> + clock-names = "xo", "alternate"; >> + >> + #freq-domain-cells = <1>; >> + #clock-cells = <1>; >> + }; >> + }; >> + >> + thermal-zones { >> + mapss-thermal { >> + polling-delay-passive = <0>; >> + polling-delay = <0>; >> + >> + thermal-sensors = <&tsens0 0>; >> + >> + trips { >> + mapss_alert0: trip-point0 { >> + temperature = <90000>; >> + hysteresis = <2000>; >> + type = "passive"; >> + }; >> + >> + mapss_alert1: trip-point1 { >> + temperature = <95000>; >> + hysteresis = <2000>; >> + type = "passive"; >> + }; >> + >> + mapss_crit: mapss-crit { >> + temperature = <110000>; >> + hysteresis = <1000>; >> + type = "critical"; >> + }; >> + }; >> + }; >> + >> + video-thermal { >> + polling-delay-passive = <0>; >> + polling-delay = <0>; >> + >> + thermal-sensors = <&tsens0 1>; >> + >> + trips { >> + video_alert0: trip-point0 { >> + temperature = <90000>; >> + hysteresis = <2000>; >> + type = "passive"; >> + }; >> + >> + video_alert1: trip-point1 { >> + temperature = <95000>; >> + hysteresis = <2000>; >> + type = "passive"; >> + }; >> + >> + video_crit: video-crit { >> + temperature = <110000>; >> + hysteresis = <1000>; >> + type = "critical"; >> + }; >> + }; >> + }; >> + >> + wlan-thermal { >> + polling-delay-passive = <0>; >> + polling-delay = <0>; >> + >> + thermal-sensors = <&tsens0 2>; >> + >> + trips { >> + wlan_alert0: trip-point0 { >> + temperature = <90000>; >> + hysteresis = <2000>; >> + type = "passive"; >> + }; >> + >> + wlan_alert1: trip-point1 { >> + temperature = <95000>; >> + hysteresis = <2000>; >> + type = "passive"; >> + }; >> + >> + wlan_crit: wlan-crit { >> + temperature = <110000>; >> + hysteresis = <1000>; >> + type = "critical"; >> + }; >> + }; >> + }; >> + >> + cpuss0-thermal { >> + polling-delay-passive = <0>; >> + polling-delay = <0>; >> + >> + thermal-sensors = <&tsens0 3>; >> + >> + trips { >> + cpuss0_alert0: trip-point0 { >> + temperature = <90000>; >> + hysteresis = <2000>; >> + type = "passive"; >> + }; >> + >> + cpuss0_alert1: trip-point1 { >> + temperature = <95000>; >> + hysteresis = <2000>; >> + type = "passive"; >> + }; >> + >> + cpuss0_crit: cpuss0-crit { >> + temperature = <110000>; >> + hysteresis = <1000>; >> + type = "critical"; >> + }; >> + }; >> + }; >> + >> + cpuss1-thermal { >> + polling-delay-passive = <0>; >> + polling-delay = <0>; >> + >> + thermal-sensors = <&tsens0 4>; >> + >> + trips { >> + cpuss1_alert0: trip-point0 { >> + temperature = <90000>; >> + hysteresis = <2000>; >> + type = "passive"; >> + }; >> + >> + cpuss1_alert1: trip-point1 { >> + temperature = <95000>; >> + hysteresis = <2000>; >> + type = "passive"; >> + }; >> + >> + cpuss1_crit: cpuss1-crit { >> + temperature = <110000>; >> + hysteresis = <1000>; >> + type = "critical"; >> + }; >> + }; >> + }; >> + >> + mdm0-thermal { >> + polling-delay-passive = <0>; >> + polling-delay = <0>; >> + >> + thermal-sensors = <&tsens0 5>; >> + >> + trips { >> + mdm0_alert0: trip-point0 { >> + temperature = <90000>; >> + hysteresis = <2000>; >> + type = "passive"; >> + }; >> + >> + mdm0_alert1: trip-point1 { >> + temperature = <95000>; >> + hysteresis = <2000>; >> + type = "passive"; >> + }; >> + >> + mdm0_crit: mdm0-crit { >> + temperature = <110000>; >> + hysteresis = <1000>; >> + type = "critical"; >> + }; >> + }; >> + }; >> + >> + mdm1-thermal { >> + polling-delay-passive = <0>; >> + polling-delay = <0>; >> + >> + thermal-sensors = <&tsens0 6>; >> + >> + trips { >> + mdm1_alert0: trip-point0 { >> + temperature = <90000>; >> + hysteresis = <2000>; >> + type = "passive"; >> + }; >> + >> + mdm1_alert1: trip-point1 { >> + temperature = <95000>; >> + hysteresis = <2000>; >> + type = "passive"; >> + }; >> + >> + mdm1_crit: mdm1-crit { >> + temperature = <110000>; >> + hysteresis = <1000>; >> + type = "critical"; >> + }; >> + }; >> + }; >> + >> + gpu-thermal { >> + polling-delay-passive = <0>; >> + polling-delay = <0>; >> + >> + thermal-sensors = <&tsens0 7>; >> + >> + trips { >> + gpu_alert0: trip-point0 { >> + temperature = <90000>; >> + hysteresis = <2000>; >> + type = "passive"; >> + }; >> + >> + gpu_alert1: trip-point1 { >> + temperature = <95000>; >> + hysteresis = <2000>; >> + type = "passive"; >> + }; >> + >> + gpu_crit: gpu-crit { >> + temperature = <110000>; >> + hysteresis = <1000>; >> + type = "critical"; >> + }; >> + }; >> + }; >> + >> + hm-center-thermal { >> + polling-delay-passive = <0>; >> + polling-delay = <0>; >> + >> + thermal-sensors = <&tsens0 8>; >> + >> + trips { >> + hm_center_alert0: trip-point0 { >> + temperature = <90000>; >> + hysteresis = <2000>; >> + type = "passive"; >> + }; >> + >> + hm_center_alert1: trip-point1 { >> + temperature = <95000>; >> + hysteresis = <2000>; >> + type = "passive"; >> + }; >> + >> + hm_center_crit: hm-center-crit { >> + temperature = <110000>; >> + hysteresis = <1000>; >> + type = "critical"; >> + }; >> + }; >> + }; >> + >> + camera-thermal { >> + polling-delay-passive = <0>; >> + polling-delay = <0>; >> + >> + thermal-sensors = <&tsens0 9>; >> + >> + trips { >> + camera_alert0: trip-point0 { >> + temperature = <90000>; >> + hysteresis = <2000>; >> + type = "passive"; >> + }; >> + >> + camera_alert1: trip-point1 { >> + temperature = <95000>; >> + hysteresis = <2000>; >> + type = "passive"; >> + }; >> + >> + camera_crit: camera-crit { >> + temperature = <110000>; >> + hysteresis = <1000>; >> + type = "critical"; >> + }; >> + }; >> + }; >> + }; >> + >> + timer { >> + compatible = "arm,armv8-timer"; >> + interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, >> + <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, >> + <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, >> + <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; >> + }; >> +}; >> >> -- >> 2.40.0 >>
diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 1a29403400b7..6fc8d6664f0c 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -70,6 +70,7 @@ dtb-$(CONFIG_ARCH_QCOM) += msm8998-xiaomi-sagit.dtb dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-1000.dtb dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-4000.dtb dtb-$(CONFIG_ARCH_QCOM) += qdu1000-idp.dtb +dtb-$(CONFIG_ARCH_QCOM) += qrb2210-rb1.dtb dtb-$(CONFIG_ARCH_QCOM) += qrb5165-rb5.dtb dtb-$(CONFIG_ARCH_QCOM) += qrb5165-rb5-vision-mezzanine.dtb dtb-$(CONFIG_ARCH_QCOM) += qru1000-idp.dtb diff --git a/arch/arm64/boot/dts/qcom/qcm2290.dtsi b/arch/arm64/boot/dts/qcom/qcm2290.dtsi new file mode 100644 index 000000000000..ae5abc76bcc7 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/qcm2290.dtsi @@ -0,0 +1,1561 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (c) 2023, Linaro Ltd + * + * Based on sm6115.dtsi and previous efforts by Shawn Guo & Loic Poulain. + */ + +#include <dt-bindings/clock/qcom,gcc-qcm2290.h> +#include <dt-bindings/clock/qcom,rpmcc.h> +#include <dt-bindings/dma/qcom-gpi.h> +#include <dt-bindings/firmware/qcom,scm.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/power/qcom-rpmpd.h> + +/ { + interrupt-parent = <&intc>; + + #address-cells = <2>; + #size-cells = <2>; + + chosen { }; + + clocks { + xo_board: xo-board { + compatible = "fixed-clock"; + #clock-cells = <0>; + }; + + sleep_clk: sleep-clk { + compatible = "fixed-clock"; + clock-frequency = <32764>; + #clock-cells = <0>; + }; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + CPU0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x0>; + clocks = <&cpufreq_hw 0>; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + qcom,freq-domain = <&cpufreq_hw 0>; + L2_0: l2-cache { + compatible = "cache"; + cache-level = <2>; + }; + }; + + CPU1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x1>; + clocks = <&cpufreq_hw 0>; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + qcom,freq-domain = <&cpufreq_hw 0>; + }; + + CPU2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x2>; + clocks = <&cpufreq_hw 0>; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + qcom,freq-domain = <&cpufreq_hw 0>; + }; + + CPU3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x3>; + clocks = <&cpufreq_hw 0>; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + qcom,freq-domain = <&cpufreq_hw 0>; + }; + + cpu-map { + cluster0 { + core0 { + cpu = <&CPU0>; + }; + + core1 { + cpu = <&CPU1>; + }; + + core2 { + cpu = <&CPU2>; + }; + + core3 { + cpu = <&CPU3>; + }; + }; + }; + }; + + firmware { + scm: scm { + compatible = "qcom,scm-qcm2290", "qcom,scm"; + clocks = <&rpmcc RPM_SMD_CE1_CLK>; + clock-names = "core"; + #reset-cells = <1>; + }; + }; + + memory@40000000 { + device_type = "memory"; + /* We expect the bootloader to fill in the size */ + reg = <0 0x40000000 0 0>; + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = <GIC_PPI 6 IRQ_TYPE_LEVEL_HIGH>; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + reserved_memory: reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + hyp_mem: hyp@45700000 { + reg = <0x0 0x45700000 0x0 0x600000>; + no-map; + }; + + xbl_aop_mem: xbl-aop@45e00000 { + reg = <0x0 0x45e00000 0x0 0x140000>; + no-map; + }; + + sec_apps_mem: sec-apps@45fff000 { + reg = <0x0 0x45fff000 0x0 0x1000>; + no-map; + }; + + smem_mem: smem@46000000 { + compatible = "qcom,smem"; + reg = <0x0 0x46000000 0x0 0x200000>; + no-map; + + hwlocks = <&tcsr_mutex 3>; + qcom,rpm-msg-ram = <&rpm_msg_ram>; + }; + + pil_modem_mem: modem@4ab00000 { + reg = <0x0 0x4ab00000 0x0 0x6900000>; + no-map; + }; + + pil_video_mem: video@51400000 { + reg = <0x0 0x51400000 0x0 0x500000>; + no-map; + }; + + wlan_msa_mem: wlan-msa@51900000 { + reg = <0x0 0x51900000 0x0 0x100000>; + no-map; + }; + + pil_adsp_mem: adsp@51a00000 { + reg = <0x0 0x51a00000 0x0 0x1c00000>; + no-map; + }; + + pil_ipa_fw_mem: ipa-fw@53600000 { + reg = <0x0 0x53600000 0x0 0x10000>; + no-map; + }; + + pil_ipa_gsi_mem: ipa-gsi@53610000 { + reg = <0x0 0x53610000 0x0 0x5000>; + no-map; + }; + + pil_gpu_mem: zap@53615000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x53615000 0x0 0x2000>; + no-map; + }; + + cont_splash_memory: framebuffer@5c000000 { + reg = <0x0 0x5c000000 0x0 0x00f00000>; + no-map; + }; + + dfps_data_memory: dpfs-data@5cf00000 { + reg = <0x0 0x5cf00000 0x0 0x0100000>; + no-map; + }; + + removed_mem: reserved@60000000 { + reg = <0x0 0x60000000 0x0 0x3900000>; + no-map; + }; + + rmtfs_mem: memory@89b01000 { + compatible = "qcom,rmtfs-mem"; + reg = <0x0 0x89b01000 0x0 0x200000>; + no-map; + + qcom,client-id = <1>; + qcom,vmid = <QCOM_SCM_VMID_MSS_MSA QCOM_SCM_VMID_NAV>; + }; + }; + + rpm-glink { + compatible = "qcom,glink-rpm"; + interrupts = <GIC_SPI 194 IRQ_TYPE_EDGE_RISING>; + qcom,rpm-msg-ram = <&rpm_msg_ram>; + mboxes = <&apcs_glb 0>; + + rpm_requests: rpm-requests { + compatible = "qcom,rpm-qcm2290"; + qcom,glink-channels = "rpm_requests"; + + rpmcc: clock-controller { + compatible = "qcom,rpmcc-qcm2290", "qcom,rpmcc"; + clocks = <&xo_board>; + clock-names = "xo"; + #clock-cells = <1>; + }; + + rpmpd: power-controller { + compatible = "qcom,qcm2290-rpmpd"; + #power-domain-cells = <1>; + operating-points-v2 = <&rpmpd_opp_table>; + + rpmpd_opp_table: opp-table { + compatible = "operating-points-v2"; + + rpmpd_opp_min_svs: opp1 { + opp-level = <RPM_SMD_LEVEL_MIN_SVS>; + }; + + rpmpd_opp_low_svs: opp2 { + opp-level = <RPM_SMD_LEVEL_LOW_SVS>; + }; + + rpmpd_opp_svs: opp3 { + opp-level = <RPM_SMD_LEVEL_SVS>; + }; + + rpmpd_opp_svs_plus: opp4 { + opp-level = <RPM_SMD_LEVEL_SVS_PLUS>; + }; + + rpmpd_opp_nom: opp5 { + opp-level = <RPM_SMD_LEVEL_NOM>; + }; + + rpmpd_opp_nom_plus: opp6 { + opp-level = <RPM_SMD_LEVEL_NOM_PLUS>; + }; + + rpmpd_opp_turbo: opp7 { + opp-level = <RPM_SMD_LEVEL_TURBO>; + }; + + rpmpd_opp_turbo_plus: opp8 { + opp-level = <RPM_SMD_LEVEL_TURBO_NO_CPR>; + }; + }; + }; + }; + }; + + smp2p-adsp { + compatible = "qcom,smp2p"; + qcom,smem = <443>, <429>; + + interrupts = <GIC_SPI 279 IRQ_TYPE_EDGE_RISING>; + + mboxes = <&apcs_glb 10>; + + qcom,local-pid = <0>; + qcom,remote-pid = <2>; + + adsp_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + adsp_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + smp2p-mpss { + compatible = "qcom,smp2p"; + qcom,smem = <435>, <428>; + + interrupts = <GIC_SPI 70 IRQ_TYPE_EDGE_RISING>; + + mboxes = <&apcs_glb 14>; + + qcom,local-pid = <0>; + qcom,remote-pid = <1>; + + modem_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + modem_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + + wlan_smp2p_in: wlan-wpss-to-ap { + qcom,entry-name = "wlan"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + soc: soc@0 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0 0 0 0 0x10 0>; + dma-ranges = <0 0 0 0 0x10 0>; + + tcsr_mutex: hwlock@340000 { + compatible = "qcom,tcsr-mutex"; + reg = <0x0 0x00340000 0x0 0x20000>; + #hwlock-cells = <1>; + }; + + tlmm: pinctrl@500000 { + compatible = "qcom,qcm2290-tlmm"; + reg = <0x0 0x00500000 0x0 0x300000>; + interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + gpio-ranges = <&tlmm 0 0 127>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + + qup_i2c0_default: qup-i2c0-default-state { + pins = "gpio0", "gpio1"; + function = "qup0"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c1_default: qup-i2c1-default-state { + pins = "gpio4", "gpio5"; + function = "qup1"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c2_default: qup-i2c2-default-state { + pins = "gpio6", "gpio7"; + function = "qup2"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c3_default: qup-i2c3-default-state { + pins = "gpio8", "gpio9"; + function = "qup3"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c4_default: qup-i2c4-default-state { + pins = "gpio12", "gpio13"; + function = "qup4"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c5_default: qup-i2c5-default-state { + pins = "gpio14", "gpio15"; + function = "qup5"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_spi0_default: qup-spi0-default-state { + pins = "gpio0", "gpio1","gpio2", "gpio3"; + function = "qup0"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_spi1_default: qup-spi1-default-state { + pins = "gpio4", "gpio5", "gpio69", "gpio70"; + function = "qup1"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_spi2_default: qup-spi2-default-state { + pins = "gpio6", "gpio7", "gpio71", "gpio80"; + function = "qup2"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_spi3_default: qup-spi3-default-state { + pins = "gpio8", "gpio9", "gpio10", "gpio11"; + function = "qup3"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_spi4_default: qup-spi4-default-state { + pins = "gpio12", "gpio13", "gpio96", "gpio97"; + function = "qup4"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_spi5_default: qup-spi5-default-state { + pins = "gpio14", "gpio15", "gpio16", "gpio17"; + function = "qup5"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_uart0_default: qup-uart0-default-state { + pins = "gpio0", "gpio1", "gpio2", "gpio3"; + function = "qup0"; + drive-strength = <2>; + bias-disable; + }; + + qup_uart4_default: qup-uart4-default-state { + pins = "gpio12", "gpio13"; + function = "qup4"; + drive-strength = <2>; + bias-disable; + }; + + sdc1_state_on: sdc1-on-state { + clk-pins { + pins = "sdc1_clk"; + drive-strength = <16>; + bias-disable; + }; + + cmd-pins { + pins = "sdc1_cmd"; + drive-strength = <10>; + bias-pull-up; + }; + + data-pins { + pins = "sdc1_data"; + drive-strength = <10>; + bias-pull-up; + }; + + rclk-pins { + pins = "sdc1_rclk"; + bias-pull-down; + }; + }; + + sdc1_state_off: sdc1-off-state { + clk-pins { + pins = "sdc1_clk"; + drive-strength = <2>; + bias-disable; + }; + + cmd-pins { + pins = "sdc1_cmd"; + drive-strength = <2>; + bias-pull-up; + }; + + data-pins { + pins = "sdc1_data"; + drive-strength = <2>; + bias-pull-up; + }; + + rclk-pins { + pins = "sdc1_rclk"; + bias-pull-down; + }; + }; + + sdc2_state_on: sdc2-on-state { + clk-pins { + pins = "sdc2_clk"; + drive-strength = <16>; + bias-disable; + }; + + cmd-pins { + pins = "sdc2_cmd"; + drive-strength = <10>; + bias-pull-up; + }; + + data-pins { + pins = "sdc2_data"; + drive-strength = <10>; + bias-pull-up; + }; + }; + + sdc2_state_off: sdc2-off-state { + clk-pins { + pins = "sdc2_clk"; + drive-strength = <2>; + bias-disable; + }; + + cmd-pins { + pins = "sdc2_cmd"; + drive-strength = <2>; + bias-pull-up; + }; + + data-pins { + pins = "sdc2_data"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + gcc: clock-controller@1400000 { + compatible = "qcom,gcc-qcm2290"; + reg = <0x0 0x01400000 0x0 0x1f0000>; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&sleep_clk>; + clock-names = "bi_tcxo", "sleep_clk"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + + usb_hsphy: phy@1613000 { + compatible = "qcom,qcm2290-qusb2-phy"; + reg = <0x0 0x01613000 0x0 0x180>; + + clocks = <&gcc GCC_AHB2PHY_USB_CLK>, + <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "cfg_ahb", "ref"; + + resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; + nvmem-cells = <&qusb2_hstx_trim>; + #phy-cells = <0>; + + status = "disabled"; + }; + + qfprom@1b44000 { + compatible = "qcom,qcm2290-qfprom", "qcom,qfprom"; + reg = <0x0 0x01b44000 0x0 0x3000>; + #address-cells = <1>; + #size-cells = <1>; + + qusb2_hstx_trim: hstx-trim@25b { + reg = <0x25b 0x1>; + bits = <1 4>; + }; + }; + + spmi_bus: spmi@1c40000 { + compatible = "qcom,spmi-pmic-arb"; + reg = <0x0 0x01c40000 0x0 0x1100>, + <0x0 0x01e00000 0x0 0x2000000>, + <0x0 0x03e00000 0x0 0x100000>, + <0x0 0x03f00000 0x0 0xa0000>, + <0x0 0x01c0a000 0x0 0x26000>; + reg-names = "core", + "chnls", + "obsrvr", + "intr", + "cnfg"; + interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "periph_irq"; + qcom,ee = <0>; + qcom,channel = <0>; + #address-cells = <2>; + #size-cells = <0>; + interrupt-controller; + #interrupt-cells = <4>; + }; + + tsens0: thermal-sensor@4411000 { + compatible = "qcom,qcm2290-tsens", "qcom,tsens-v2"; + reg = <0x0 0x04411000 0x0 0x1ff>, + <0x0 0x04410000 0x0 0x8>; + #qcom,sensors = <10>; + interrupts = <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "uplow", "critical"; + #thermal-sensor-cells = <1>; + }; + + rng: rng@4453000 { + compatible = "qcom,prng-ee"; + reg = <0x0 0x04453000 0x0 0x1000>; + clocks = <&rpmcc RPM_SMD_HWKM_CLK>; + clock-names = "core"; + }; + + rpm_msg_ram: sram@45f0000 { + compatible = "qcom,rpm-msg-ram"; + reg = <0x0 0x045f0000 0x0 0x7000>; + }; + + sram@4690000 { + compatible = "qcom,rpm-stats"; + reg = <0x0 0x04690000 0x0 0x10000>; + }; + + sdhc_1: mmc@4744000 { + compatible = "qcom,qcm2290-sdhci", "qcom,sdhci-msm-v5"; + reg = <0x0 0x04744000 0x0 0x1000>, + <0x0 0x04745000 0x0 0x1000>, + <0x0 0x04748000 0x0 0x8000>; + reg-names = "hc", + "cqhci", + "ice"; + + interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "hc_irq", "pwr_irq"; + + clocks = <&gcc GCC_SDCC1_AHB_CLK>, + <&gcc GCC_SDCC1_APPS_CLK>, + <&rpmcc RPM_SMD_XO_CLK_SRC>, + <&gcc GCC_SDCC1_ICE_CORE_CLK>; + clock-names = "iface", + "core", + "xo", + "ice"; + + resets = <&gcc GCC_SDCC1_BCR>; + + power-domains = <&rpmpd QCM2290_VDDCX>; + iommus = <&apps_smmu 0xc0 0x0>; + + qcom,dll-config = <0x000f642c>; + qcom,ddr-config = <0x80040868>; + bus-width = <8>; + + status = "disabled"; + }; + + sdhc_2: mmc@4784000 { + compatible = "qcom,qcm2290-sdhci", "qcom,sdhci-msm-v5"; + reg = <0x0 0x04784000 0x0 0x1000>; + reg-names = "hc"; + + interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "hc_irq", "pwr_irq"; + + clocks = <&gcc GCC_SDCC2_AHB_CLK>, + <&gcc GCC_SDCC2_APPS_CLK>, + <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "iface", + "core", + "xo"; + + resets = <&gcc GCC_SDCC2_BCR>; + + power-domains = <&rpmpd QCM2290_VDDCX>; + operating-points-v2 = <&sdhc2_opp_table>; + iommus = <&apps_smmu 0xa0 0x0>; + + qcom,dll-config = <0x0007642c>; + qcom,ddr-config = <0x80040868>; + bus-width = <4>; + + status = "disabled"; + + sdhc2_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + required-opps = <&rpmpd_opp_low_svs>; + }; + + opp-202000000 { + opp-hz = /bits/ 64 <202000000>; + required-opps = <&rpmpd_opp_svs_plus>; + }; + }; + }; + + gpi_dma0: dma-controller@4a00000 { + compatible = "qcom,qcm2290-gpi-dma", "qcom,sm6350-gpi-dma"; + reg = <0x0 0x04a00000 0x0 0x60000>; + interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>; + dma-channels = <10>; + dma-channel-mask = <0x1f>; + iommus = <&apps_smmu 0xf6 0x0>; + #dma-cells = <3>; + status = "disabled"; + }; + + qupv3_id_0: geniqup@4ac0000 { + compatible = "qcom,geni-se-qup"; + reg = <0x0 0x04ac0000 0x0 0x2000>; + clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + clock-names = "m-ahb", "s-ahb"; + iommus = <&apps_smmu 0xe3 0x0>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + + i2c0: i2c@4a80000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x04a80000 0x0 0x4000>; + interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; + clock-names = "se"; + pinctrl-0 = <&qup_i2c0_default>; + pinctrl-names = "default"; + dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, + <&gpi_dma0 1 0 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi0: spi@4a80000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x04a80000 0x0 0x4000>; + interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; + clock-names = "se"; + pinctrl-0 = <&qup_spi0_default>; + pinctrl-names = "default"; + dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, + <&gpi_dma0 1 0 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + uart0: serial@4a80000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0x04a80000 0x0 0x4000>; + interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; + clock-names = "se"; + pinctrl-0 = <&qup_uart0_default>; + pinctrl-names = "default"; + status = "disabled"; + }; + + i2c1: i2c@4a84000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x04a84000 0x0 0x4000>; + interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; + clock-names = "se"; + pinctrl-0 = <&qup_i2c1_default>; + pinctrl-names = "default"; + dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, + <&gpi_dma0 1 1 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi1: spi@4a84000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x04a84000 0x0 0x4000>; + interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; + clock-names = "se"; + pinctrl-0 = <&qup_spi1_default>; + pinctrl-names = "default"; + dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, + <&gpi_dma0 1 1 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@4a88000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x04a88000 0x0 0x4000>; + interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; + clock-names = "se"; + pinctrl-0 = <&qup_i2c2_default>; + pinctrl-names = "default"; + dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, + <&gpi_dma0 1 2 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi2: spi@4a88000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x04a88000 0x0 0x4000>; + interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; + clock-names = "se"; + pinctrl-0 = <&qup_spi2_default>; + pinctrl-names = "default"; + dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, + <&gpi_dma0 1 2 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c3: i2c@4a8c000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x04a8c000 0x0 0x4000>; + interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; + clock-names = "se"; + pinctrl-0 = <&qup_i2c3_default>; + pinctrl-names = "default"; + dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, + <&gpi_dma0 1 3 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi3: spi@4a8c000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x04a8c000 0x0 0x4000>; + interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; + clock-names = "se"; + pinctrl-0 = <&qup_spi3_default>; + pinctrl-names = "default"; + dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, + <&gpi_dma0 1 3 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c4: i2c@4a90000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x04a90000 0x0 0x4000>; + interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; + clock-names = "se"; + pinctrl-0 = <&qup_i2c4_default>; + pinctrl-names = "default"; + dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, + <&gpi_dma0 1 4 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi4: spi@4a90000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x04a90000 0x0 0x4000>; + interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi4_default>; + dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, + <&gpi_dma0 1 4 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + uart4: serial@4a90000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0x04a90000 0x0 0x4000>; + interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; + clock-names = "se"; + pinctrl-0 = <&qup_uart4_default>; + pinctrl-names = "default"; + status = "disabled"; + }; + + i2c5: i2c@4a94000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x04a94000 0x0 0x4000>; + interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; + clock-names = "se"; + pinctrl-0 = <&qup_i2c5_default>; + pinctrl-names = "default"; + dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, + <&gpi_dma0 1 5 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi5: spi@4a94000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x04a94000 0x0 0x4000>; + interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; + clock-names = "se"; + pinctrl-0 = <&qup_spi5_default>; + pinctrl-names = "default"; + dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, + <&gpi_dma0 1 5 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + + usb: usb@4ef8800 { + compatible = "qcom,qcm2290-dwc3", "qcom,dwc3"; + reg = <0x0 0x04ef8800 0x0 0x400>; + interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "hs_phy_irq", "ss_phy_irq"; + + clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_MASTER_CLK>, + <&gcc GCC_SYS_NOC_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_SLEEP_CLK>, + <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, + <&gcc GCC_USB3_PRIM_CLKREF_CLK>; + clock-names = "cfg_noc", + "core", + "iface", + "sleep", + "mock_utmi", + "xo"; + + assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_PRIM_MASTER_CLK>; + assigned-clock-rates = <19200000>, <133333333>; + + resets = <&gcc GCC_USB30_PRIM_BCR>; + power-domains = <&gcc GCC_USB30_PRIM_GDSC>; + wakeup-source; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + status = "disabled"; + + usb_dwc3: usb@4e00000 { + compatible = "snps,dwc3"; + reg = <0x0 0x04e00000 0x0 0xcd00>; + interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; + phys = <&usb_hsphy>; + phy-names = "usb2-phy"; + iommus = <&apps_smmu 0x120 0x0>; + snps,dis_u2_susphy_quirk; + snps,dis_enblslpm_quirk; + snps,has-lpm-erratum; + snps,hird-threshold = /bits/ 8 <0x10>; + snps,usb3_lpm_capable; + maximum-speed = "super-speed"; + dr_mode = "otg"; + }; + }; + + remoteproc_mpss: remoteproc@6080000 { + compatible = "qcom,qcm2290-mpss-pas", "qcom,sm6115-mpss-pas"; + reg = <0x0 0x06080000 0x0 0x100>; + + interrupts-extended = <&intc GIC_SPI 307 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", + "fatal", + "ready", + "handover", + "stop-ack", + "shutdown-ack"; + + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "xo"; + + power-domains = <&rpmpd QCM2290_VDDCX>; + + memory-region = <&pil_modem_mem>; + + qcom,smem-states = <&modem_smp2p_out 0>; + qcom,smem-state-names = "stop"; + + status = "disabled"; + + glink-edge { + interrupts = <GIC_SPI 68 IRQ_TYPE_EDGE_RISING>; + label = "mpss"; + qcom,remote-pid = <1>; + mboxes = <&apcs_glb 12>; + }; + }; + + remoteproc_adsp: remoteproc@ab00000 { + compatible = "qcom,qcm2290-adsp-pas", "qcom,sm6115-adsp-pas"; + reg = <0x0 0x0ab00000 0x0 0x100>; + + interrupts-extended = <&intc GIC_SPI 282 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", + "fatal", + "ready", + "handover", + "stop-ack"; + + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "xo"; + + power-domains = <&rpmpd QCM2290_VDD_LPI_CX>, + <&rpmpd QCM2290_VDD_LPI_MX>; + + memory-region = <&pil_adsp_mem>; + + qcom,smem-states = <&adsp_smp2p_out 0>; + qcom,smem-state-names = "stop"; + + status = "disabled"; + + glink-edge { + interrupts = <GIC_SPI 277 IRQ_TYPE_EDGE_RISING>; + label = "lpass"; + qcom,remote-pid = <2>; + mboxes = <&apcs_glb 8>; + }; + }; + + apps_smmu: iommu@c600000 { + compatible = "qcom,qcm2290-smmu-500", "qcom,smmu-500", "arm,mmu-500"; + reg = <0x0 0x0c600000 0x0 0x80000>; + #iommu-cells = <2>; + #global-interrupts = <1>; + + interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; + }; + + wifi: wifi@c800000 { + compatible = "qcom,wcn3990-wifi"; + reg = <0x0 0x0c800000 0x0 0x800000>; + reg-names = "membase"; + memory-region = <&wlan_msa_mem>; + interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; + iommus = <&apps_smmu 0x1a0 0x1>; + qcom,msa-fixed-perm; + status = "disabled"; + }; + + watchdog@f017000 { + compatible = "qcom,apss-wdt-qcm2290", "qcom,kpss-wdt"; + reg = <0x0 0x0f017000 0x0 0x1000>; + interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&sleep_clk>; + }; + + apcs_glb: mailbox@f111000 { + compatible = "qcom,qcm2290-apcs-hmss-global"; + reg = <0x0 0x0f111000 0x0 0x1000>; + #mbox-cells = <1>; + }; + + timer@f120000 { + compatible = "arm,armv7-timer-mem"; + reg = <0x0 0x0f120000 0x0 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x0 0x0f121000 0x8000>; + + frame@0 { + reg = <0x0 0x1000>, + <0x1000 0x1000>; + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; + frame-number = <0>; + }; + + frame@2000 { + reg = <0x2000 0x1000>; + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; + frame-number = <1>; + status = "disabled"; + }; + + frame@3000 { + reg = <0x3000 0x1000>; + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; + frame-number = <2>; + status = "disabled"; + }; + + frame@4000 { + reg = <0x4000 0x1000>; + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; + frame-number = <3>; + status = "disabled"; + }; + + frame@5000 { + reg = <0x5000 0x1000>; + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; + frame-number = <4>; + status = "disabled"; + }; + + frame@6000 { + reg = <0x6000 0x1000>; + interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; + frame-number = <5>; + status = "disabled"; + }; + + frame@7000 { + reg = <0x7000 0x1000>; + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; + frame-number = <6>; + status = "disabled"; + }; + }; + + intc: interrupt-controller@f200000 { + compatible = "arm,gic-v3"; + reg = <0x0 0x0f200000 0x0 0x10000>, + <0x0 0x0f300000 0x0 0x100000>; + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; + #interrupt-cells = <3>; + interrupt-controller; + interrupt-parent = <&intc>; + #redistributor-regions = <1>; + redistributor-stride = <0x0 0x20000>; + }; + + cpufreq_hw: cpufreq@f521000 { + compatible = "qcom,qcm2290-cpufreq-hw", "qcom,cpufreq-hw"; + reg = <0x0 0x0f521000 0x0 0x1000>; + reg-names = "freq-domain0"; + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "dcvsh-irq-0"; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GPLL0>; + clock-names = "xo", "alternate"; + + #freq-domain-cells = <1>; + #clock-cells = <1>; + }; + }; + + thermal-zones { + mapss-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&tsens0 0>; + + trips { + mapss_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + mapss_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + mapss_crit: mapss-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + video-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&tsens0 1>; + + trips { + video_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + video_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + video_crit: video-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + wlan-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&tsens0 2>; + + trips { + wlan_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + wlan_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + wlan_crit: wlan-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpuss0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&tsens0 3>; + + trips { + cpuss0_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpuss0_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpuss0_crit: cpuss0-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpuss1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&tsens0 4>; + + trips { + cpuss1_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpuss1_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpuss1_crit: cpuss1-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + mdm0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&tsens0 5>; + + trips { + mdm0_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + mdm0_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + mdm0_crit: mdm0-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + mdm1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&tsens0 6>; + + trips { + mdm1_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + mdm1_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + mdm1_crit: mdm1-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + gpu-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&tsens0 7>; + + trips { + gpu_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + gpu_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + gpu_crit: gpu-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + hm-center-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&tsens0 8>; + + trips { + hm_center_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + hm_center_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + hm_center_crit: hm-center-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + camera-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&tsens0 9>; + + trips { + camera_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + camera_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + camera_crit: camera-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; + }; +};
Add an initial device tree for the QCM2290 low-end SoC, featuring 4 "customized" Cortex-A53 cores and up to 4 GiB of LPDDR(3/4X). This revision brings support for: - TSENS & thermal zones - SDHCI1/2 - I2C, SPI, UART - MPSS - ADSP - Wi-Fi Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> --- arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/qcm2290.dtsi | 1561 +++++++++++++++++++++++++++++++++ 2 files changed, 1562 insertions(+)