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[07/10] clocksource/drivers/arm_arch_timer: Add dt binding for hisilicon-161010101 erratum

Message ID 1486595685-10232-7-git-send-email-daniel.lezcano@linaro.org
State Accepted
Commit 729e55225b1f6225ee7a2a358d5141a3264627c4
Headers show
Series [01/10] clockevents: Add a clkevt-of mechanism like clksrc-of | expand

Commit Message

Daniel Lezcano Feb. 8, 2017, 11:14 p.m. UTC 
From: Ding Tianhong <dingtianhong@huawei.com>


This erratum describes a bug in logic outside the core, so MIDR can't be
used to identify its presence, and reading an SoC-specific revision
register from common arch timer code would be awkward.  So, describe it
in the device tree.

Signed-off-by: Ding Tianhong <dingtianhong@huawei.com>

Acked-by: Rob Herring <robh@kernel.org>

Signed-off-by: Mark Rutland <mark.rutland@arm.com>

Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>

---
 Documentation/devicetree/bindings/arm/arch_timer.txt | 6 ++++++
 1 file changed, 6 insertions(+)

-- 
2.7.4
diff mbox series

Patch

diff --git a/Documentation/devicetree/bindings/arm/arch_timer.txt b/Documentation/devicetree/bindings/arm/arch_timer.txt
index ad440a2..e926aea 100644
--- a/Documentation/devicetree/bindings/arm/arch_timer.txt
+++ b/Documentation/devicetree/bindings/arm/arch_timer.txt
@@ -31,6 +31,12 @@  to deliver its interrupts via SPIs.
   This also affects writes to the tval register, due to the implicit
   counter read.
 
+- hisilicon,erratum-161010101 : A boolean property. Indicates the
+  presence of Hisilicon erratum 161010101, which says that reading the
+  counters is unreliable in some cases, and reads may return a value 32
+  beyond the correct value. This also affects writes to the tval
+  registers, due to the implicit counter read.
+
 ** Optional properties:
 
 - arm,cpu-registers-not-fw-configured : Firmware does not initialize