Message ID | 1488218551-6372-2-git-send-email-ard.biesheuvel@linaro.org |
---|---|
State | New |
Headers | show |
Series | AMD/Styx: enable strict memory permissions | expand |
On 27 February 2017 at 18:02, Ard Biesheuvel <ard.biesheuvel@linaro.org> wrote: > Remove the code from PlatformSmbiosDxe that writes to a string literal > to turn the string 'L# Cache' into L1/L2/L3, and just emit the three > versions instead. This is necessary given that string literals are > emitted into .rodata by default, which makes them read-only when strict > memory permissions are in effect. > > Contributed-under: TianoCore Contribution Agreement 1.0 > Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> > --- > Platforms/AMD/Styx/Drivers/PlatformSmbiosDxe/PlatformSmbiosDxe.c | 21 ++++++++++++-------- > 1 file changed, 13 insertions(+), 8 deletions(-) > > diff --git a/Platforms/AMD/Styx/Drivers/PlatformSmbiosDxe/PlatformSmbiosDxe.c b/Platforms/AMD/Styx/Drivers/PlatformSmbiosDxe/PlatformSmbiosDxe.c > index 5ee5d92fdf9c..14e3cc409dbc 100644 > --- a/Platforms/AMD/Styx/Drivers/PlatformSmbiosDxe/PlatformSmbiosDxe.c > +++ b/Platforms/AMD/Styx/Drivers/PlatformSmbiosDxe/PlatformSmbiosDxe.c > @@ -355,8 +355,16 @@ SMBIOS_TABLE_TYPE7 mCacheInfoType7 = { > CacheAssociativity2Way // Associativity > }; > #if (FixedPcdGetBool (PcdIscpSupport)) > -CHAR8 *mCacheInfoType7Strings[] = { > - "L# Cache", > +CHAR8 *mCacheInfoType7StringsL1[] = { > + "L1 Cache", > + NULL > +}; > +CHAR8 *mCacheInfoType7StringsL2[] = { > + "L2 Cache", > + NULL > +}; > +CHAR8 *mCacheInfoType7StringsL3[] = { > + "L3 Cache", > NULL > }; Actually, this is a bit overkill: we can simply keep a single version and assign a different char pointer to element 0 for each of L1, L2 and L3 cache rather than update the digit 3 times. > #else > @@ -710,7 +718,6 @@ CacheInfoUpdateSmbiosType7 ( > dstType7.SocketDesignation = 1; // "L# Cache" > > // L1 cache settings > - mCacheInfoType7Strings[0][1] = '1'; // "L# Cache" --> "L1 Cache" > SmbiosT7 = &mSmbiosInfo.SmbiosCpuBuffer.T7L1[0]; > dstType7.CacheConfiguration = SmbiosT7->T7CacheCfg; > dstType7.MaximumCacheSize = SmbiosT7->T7MaxCacheSize; > @@ -723,10 +730,9 @@ CacheInfoUpdateSmbiosType7 ( > dstType7.ErrorCorrectionType = SmbiosT7->T7ErrorCorrectionType; > dstType7.SystemCacheType = SmbiosT7->T7SystemCacheType; > dstType7.Associativity = SmbiosT7->T7Associativity; > - LogSmbiosData ((EFI_SMBIOS_TABLE_HEADER *)&dstType7, mCacheInfoType7Strings); > + LogSmbiosData ((EFI_SMBIOS_TABLE_HEADER *)&dstType7, mCacheInfoType7StringsL1); > > // L2 cache settings > - mCacheInfoType7Strings[0][1] = '2'; // "L# Cache" --> "L2 Cache" > SmbiosT7 = &mSmbiosInfo.SmbiosCpuBuffer.T7L2[0]; > dstType7.CacheConfiguration = SmbiosT7->T7CacheCfg; > dstType7.MaximumCacheSize = SmbiosT7->T7MaxCacheSize; > @@ -739,10 +745,9 @@ CacheInfoUpdateSmbiosType7 ( > dstType7.ErrorCorrectionType = SmbiosT7->T7ErrorCorrectionType; > dstType7.SystemCacheType = SmbiosT7->T7SystemCacheType; > dstType7.Associativity = SmbiosT7->T7Associativity; > - LogSmbiosData ((EFI_SMBIOS_TABLE_HEADER *)&dstType7, mCacheInfoType7Strings); > + LogSmbiosData ((EFI_SMBIOS_TABLE_HEADER *)&dstType7, mCacheInfoType7StringsL2); > > // L3 cache settings > - mCacheInfoType7Strings[0][1] = '3'; // "L# Cache" --> "L3 Cache" > SmbiosT7 = &mSmbiosInfo.SmbiosCpuBuffer.T7L3[0]; > dstType7.CacheConfiguration = SmbiosT7->T7CacheCfg; > dstType7.MaximumCacheSize = SmbiosT7->T7MaxCacheSize; > @@ -755,7 +760,7 @@ CacheInfoUpdateSmbiosType7 ( > dstType7.ErrorCorrectionType = SmbiosT7->T7ErrorCorrectionType; > dstType7.SystemCacheType = SmbiosT7->T7SystemCacheType; > dstType7.Associativity = SmbiosT7->T7Associativity; > - LogSmbiosData ((EFI_SMBIOS_TABLE_HEADER *)&dstType7, mCacheInfoType7Strings); > + LogSmbiosData ((EFI_SMBIOS_TABLE_HEADER *)&dstType7, mCacheInfoType7StringsL3); > #else > LogSmbiosData ((EFI_SMBIOS_TABLE_HEADER *)&mCacheInfoType7, mCacheInfoType7Strings); > #endif > -- > 2.7.4 >
diff --git a/Platforms/AMD/Styx/Drivers/PlatformSmbiosDxe/PlatformSmbiosDxe.c b/Platforms/AMD/Styx/Drivers/PlatformSmbiosDxe/PlatformSmbiosDxe.c index 5ee5d92fdf9c..14e3cc409dbc 100644 --- a/Platforms/AMD/Styx/Drivers/PlatformSmbiosDxe/PlatformSmbiosDxe.c +++ b/Platforms/AMD/Styx/Drivers/PlatformSmbiosDxe/PlatformSmbiosDxe.c @@ -355,8 +355,16 @@ SMBIOS_TABLE_TYPE7 mCacheInfoType7 = { CacheAssociativity2Way // Associativity }; #if (FixedPcdGetBool (PcdIscpSupport)) -CHAR8 *mCacheInfoType7Strings[] = { - "L# Cache", +CHAR8 *mCacheInfoType7StringsL1[] = { + "L1 Cache", + NULL +}; +CHAR8 *mCacheInfoType7StringsL2[] = { + "L2 Cache", + NULL +}; +CHAR8 *mCacheInfoType7StringsL3[] = { + "L3 Cache", NULL }; #else @@ -710,7 +718,6 @@ CacheInfoUpdateSmbiosType7 ( dstType7.SocketDesignation = 1; // "L# Cache" // L1 cache settings - mCacheInfoType7Strings[0][1] = '1'; // "L# Cache" --> "L1 Cache" SmbiosT7 = &mSmbiosInfo.SmbiosCpuBuffer.T7L1[0]; dstType7.CacheConfiguration = SmbiosT7->T7CacheCfg; dstType7.MaximumCacheSize = SmbiosT7->T7MaxCacheSize; @@ -723,10 +730,9 @@ CacheInfoUpdateSmbiosType7 ( dstType7.ErrorCorrectionType = SmbiosT7->T7ErrorCorrectionType; dstType7.SystemCacheType = SmbiosT7->T7SystemCacheType; dstType7.Associativity = SmbiosT7->T7Associativity; - LogSmbiosData ((EFI_SMBIOS_TABLE_HEADER *)&dstType7, mCacheInfoType7Strings); + LogSmbiosData ((EFI_SMBIOS_TABLE_HEADER *)&dstType7, mCacheInfoType7StringsL1); // L2 cache settings - mCacheInfoType7Strings[0][1] = '2'; // "L# Cache" --> "L2 Cache" SmbiosT7 = &mSmbiosInfo.SmbiosCpuBuffer.T7L2[0]; dstType7.CacheConfiguration = SmbiosT7->T7CacheCfg; dstType7.MaximumCacheSize = SmbiosT7->T7MaxCacheSize; @@ -739,10 +745,9 @@ CacheInfoUpdateSmbiosType7 ( dstType7.ErrorCorrectionType = SmbiosT7->T7ErrorCorrectionType; dstType7.SystemCacheType = SmbiosT7->T7SystemCacheType; dstType7.Associativity = SmbiosT7->T7Associativity; - LogSmbiosData ((EFI_SMBIOS_TABLE_HEADER *)&dstType7, mCacheInfoType7Strings); + LogSmbiosData ((EFI_SMBIOS_TABLE_HEADER *)&dstType7, mCacheInfoType7StringsL2); // L3 cache settings - mCacheInfoType7Strings[0][1] = '3'; // "L# Cache" --> "L3 Cache" SmbiosT7 = &mSmbiosInfo.SmbiosCpuBuffer.T7L3[0]; dstType7.CacheConfiguration = SmbiosT7->T7CacheCfg; dstType7.MaximumCacheSize = SmbiosT7->T7MaxCacheSize; @@ -755,7 +760,7 @@ CacheInfoUpdateSmbiosType7 ( dstType7.ErrorCorrectionType = SmbiosT7->T7ErrorCorrectionType; dstType7.SystemCacheType = SmbiosT7->T7SystemCacheType; dstType7.Associativity = SmbiosT7->T7Associativity; - LogSmbiosData ((EFI_SMBIOS_TABLE_HEADER *)&dstType7, mCacheInfoType7Strings); + LogSmbiosData ((EFI_SMBIOS_TABLE_HEADER *)&dstType7, mCacheInfoType7StringsL3); #else LogSmbiosData ((EFI_SMBIOS_TABLE_HEADER *)&mCacheInfoType7, mCacheInfoType7Strings); #endif
Remove the code from PlatformSmbiosDxe that writes to a string literal to turn the string 'L# Cache' into L1/L2/L3, and just emit the three versions instead. This is necessary given that string literals are emitted into .rodata by default, which makes them read-only when strict memory permissions are in effect. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> --- Platforms/AMD/Styx/Drivers/PlatformSmbiosDxe/PlatformSmbiosDxe.c | 21 ++++++++++++-------- 1 file changed, 13 insertions(+), 8 deletions(-)