Message ID | 20240426-a750-raytracing-v2-0-562ac9866d63@gmail.com |
---|---|
Headers | show |
Series | drm/msm: Support a750 "software fuse" for raytracing | expand |
On Fri, 26 Apr 2024 at 21:34, Connor Abbott <cwabbott0@gmail.com> wrote: > > This is doubled compared to previous GPUs. We can't access the new > SW_FUSE_VALUE register without this. > > Fixes: db33633b05c0 ("arm64: dts: qcom: sm8650: add GPU nodes") > Signed-off-by: Connor Abbott <cwabbott0@gmail.com> > --- > arch/arm64/boot/dts/qcom/sm8650.dtsi | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
On Fri, 26 Apr 2024 at 21:34, Connor Abbott <cwabbott0@gmail.com> wrote: > > Update to mesa commit ff155f46a33 ("freedreno/a7xx: Register updates > from kgsl"). > > Signed-off-by: Connor Abbott <cwabbott0@gmail.com> > --- > drivers/gpu/drm/msm/registers/adreno/a6xx.xml | 28 ++++++++++++++++++++++++--- > 1 file changed, 25 insertions(+), 3 deletions(-) Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
On Fri, 26 Apr 2024 at 21:34, Connor Abbott <cwabbott0@gmail.com> wrote: > > Expose the value of the software fuse to userspace. > > Signed-off-by: Connor Abbott <cwabbott0@gmail.com> > --- > drivers/gpu/drm/msm/adreno/adreno_gpu.c | 3 +++ > include/uapi/drm/msm_drm.h | 1 + > 2 files changed, 4 insertions(+) Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
On 26.04.2024 8:33 PM, Connor Abbott wrote: > This is doubled compared to previous GPUs. We can't access the new > SW_FUSE_VALUE register without this. > > Fixes: db33633b05c0 ("arm64: dts: qcom: sm8650: add GPU nodes") > Signed-off-by: Connor Abbott <cwabbott0@gmail.com> > --- Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Konrad
On 26.04.2024 8:34 PM, Connor Abbott wrote: > Expose the value of the software fuse to userspace. > > Signed-off-by: Connor Abbott <cwabbott0@gmail.com> > --- > drivers/gpu/drm/msm/adreno/adreno_gpu.c | 3 +++ > include/uapi/drm/msm_drm.h | 1 + > 2 files changed, 4 insertions(+) > > diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c > index 074fb498706f..99ad651857b2 100644 > --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c > +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c > @@ -376,6 +376,9 @@ int adreno_get_param(struct msm_gpu *gpu, struct msm_file_private *ctx, > case MSM_PARAM_HIGHEST_BANK_BIT: > *value = adreno_gpu->ubwc_config.highest_bank_bit; > return 0; > + case MSM_PARAM_RAYTRACING: > + *value = adreno_gpu->has_ray_tracing; > + return 0; I'd personally go with MSM_PARAM_FEATURES as a u64 bitmap, but it's not me that'll have to deal with this on the userland side, so: Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Konrad
On Fri, 26 Apr 2024 19:33:58 +0100, Connor Abbott wrote: > On a750, Qualcomm decided to gate support for certain features behind a > "software fuse." This consists of a register in the cx_mem zone, which > is normally only writeable by the TrustZone firmware. On bootup it is > 0, and we must call an SCM method to initialize it. Then we communicate > its value to userspace. This implements all of this, copying the SCM > call from the downstream kernel and kgsl. > > [...] Applied, thanks! [1/6] arm64: dts: qcom: sm8650: Fix GPU cx_mem size commit: 0d80ac75cba26fde5cae55323b7617f0fec5322b Best regards,