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[v5,RESEND,0/4] ncrease ecam size value to discover 256 buses during

Message ID 20231005164051.984254-1-thippeswamy.havalige@amd.com
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Series ncrease ecam size value to discover 256 buses during | expand

Message

Havalige, Thippeswamy Oct. 5, 2023, 4:40 p.m. UTC 
Current driver is supports up to 16 buses. The following code fixes 
to support up to 256 buses.

update "NWL_ECAM_VALUE_DEFAULT " to 16  can access up to 256MB ECAM
region to detect 256 buses.

Update ecam size to 256MB in device tree binding example.

Remove unwanted code.

Thippeswamy Havalige (4):
  PCI: xilinx-nwl: Remove unnecessary code which updates primary,
    secondary and sub-ordinate bus numbers
  dt-bindings: PCI: xilinx-nwl: Modify ECAM size in example
  PCI: xilinx-nwl: Rename ECAM size default macro
  PCI: xilinx-nwl: Increase ECAM size to accommodate 256 buses

 .../devicetree/bindings/pci/xlnx,nwl-pcie.yaml |  2 +-
 drivers/pci/controller/pcie-xilinx-nwl.c       | 18 +++---------------
 2 files changed, 4 insertions(+), 16 deletions(-)