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Show patches with
: Submitter =
Havalige, Thippeswamy
| State =
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| Archived =
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| 8 patches
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andy.doan@linaro.org
andy.doan@linaro.org
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[v5,RESEND,4/4] PCI: xilinx-nwl: Increase ECAM size to accommodate 256 buses
increase ecam size value to discover 256 buses during
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2023-10-16
Havalige, Thippeswamy
New
[v5,RESEND,1/4] PCI: xilinx-nwl: Remove unnecessary code which updates primary, secondary and sub-ordinate bus numbers
increase ecam size value to discover 256 buses during
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2023-10-16
Havalige, Thippeswamy
New
[v5,RESEND,3/4] PCI: xilinx-nwl: Rename ECAM size default macro
ncrease ecam size value to discover 256 buses during
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2023-10-05
Havalige, Thippeswamy
New
[v1,1/2] PCI: xilinx-nwl: Update ECAM default value and remove unnecessary code.
Fix ecam size value to discover 256 buses during
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2023-08-07
Havalige, Thippeswamy
New
[v4,3/3] PCI: xilinx-xdma: Add Xilinx XDMA Root Port driver
[v4,1/3] Move and rename error interrupt bits to a common header.
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2023-05-31
Havalige, Thippeswamy
New
[v4,1/3] Move and rename error interrupt bits to a common header.
[v4,1/3] Move and rename error interrupt bits to a common header.
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2023-05-31
Havalige, Thippeswamy
New
[v2,3/3] PCI: xilinx-xdma: Add Xilinx XDMA Root Port driver
[v2,1/3] Move error interrupt bits to a common header.
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2023-05-12
Havalige, Thippeswamy
New
[2/2] PCI: xilinx-xdma: Add Xilinx XDMA Root Port driver
Add support for Xilinx XDMA Soft IP as Root Port.
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2023-04-17
Havalige, Thippeswamy
New