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ncrease ecam size value to discover 256 buses during
| 4 patches
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andy.doan@linaro.org
andy.doan@linaro.org
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[v5,RESEND,4/4] PCI: xilinx-nwl: Increase ECAM size to accommodate 256 buses
ncrease ecam size value to discover 256 buses during
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2023-10-05
Havalige, Thippeswamy
Superseded
[v5,RESEND,3/4] PCI: xilinx-nwl: Rename ECAM size default macro
ncrease ecam size value to discover 256 buses during
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2023-10-05
Havalige, Thippeswamy
New
[v5,RESEND,2/4] dt-bindings: PCI: xilinx-nwl: Modify ECAM size in example
ncrease ecam size value to discover 256 buses during
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2023-10-05
Havalige, Thippeswamy
Accepted
[v5,RESEND,1/4] PCI: xilinx-nwl: Remove unnecessary code which updates primary, secondary and sub-ordinate bus numbers
ncrease ecam size value to discover 256 buses during
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2023-10-05
Havalige, Thippeswamy
Superseded