Show patches with: Submitter = Havalige, Thippeswamy       |    Archived = No       |   34 patches
Patch Series S/W/F Date Submitter Delegate State
[v5,RESEND,4/4] PCI: xilinx-nwl: Increase ECAM size to accommodate 256 buses increase ecam size value to discover 256 buses during --- 2023-10-16 Havalige, Thippeswamy New
[v5,RESEND,1/4] PCI: xilinx-nwl: Remove unnecessary code which updates primary, secondary and sub-ordinate bus numbers increase ecam size value to discover 256 buses during --- 2023-10-16 Havalige, Thippeswamy New
[v5,RESEND,4/4] PCI: xilinx-nwl: Increase ECAM size to accommodate 256 buses ncrease ecam size value to discover 256 buses during --- 2023-10-05 Havalige, Thippeswamy Superseded
[v5,RESEND,3/4] PCI: xilinx-nwl: Rename ECAM size default macro ncrease ecam size value to discover 256 buses during --- 2023-10-05 Havalige, Thippeswamy New
[v5,RESEND,2/4] dt-bindings: PCI: xilinx-nwl: Modify ECAM size in example ncrease ecam size value to discover 256 buses during --- 2023-10-05 Havalige, Thippeswamy Accepted
[v5,RESEND,1/4] PCI: xilinx-nwl: Remove unnecessary code which updates primary, secondary and sub-ordinate bus numbers ncrease ecam size value to discover 256 buses during --- 2023-10-05 Havalige, Thippeswamy Superseded
[v7,RESEND,3/3] PCI: xilinx-xdma: Add Xilinx XDMA Root Port driver Add support for Xilinx XDMA Soft IP as Root Port. --- 2023-10-03 Havalige, Thippeswamy Accepted
[v7,RESEND,2/3] dt-bindings: PCI: xilinx-xdma: Add YAML schemas for Xilinx XDMA PCIe Root Port Bridge Add support for Xilinx XDMA Soft IP as Root Port. --- 2023-10-03 Havalige, Thippeswamy Accepted
[v7,RESEND,1/3] PCI: xilinx-cpm: Move interrupt bit definitions to common header Add support for Xilinx XDMA Soft IP as Root Port. --- 2023-10-03 Havalige, Thippeswamy Accepted
[v7,3/3] PCI: xilinx-xdma: Add Xilinx XDMA Root Port driver Add support for Xilinx XDMA Soft IP as Root Port. --- 2023-08-30 Havalige, Thippeswamy Superseded
[v7,2/3] dt-bindings: PCI: xilinx-xdma: Add YAML schemas for Xilinx XDMA PCIe Root Port Bridge Add support for Xilinx XDMA Soft IP as Root Port. --- 2023-08-30 Havalige, Thippeswamy Superseded
[v7,1/3] PCI: xilinx-cpm: Move interrupt bit definitions to common header Add support for Xilinx XDMA Soft IP as Root Port. --- 2023-08-30 Havalige, Thippeswamy Superseded
[v6,1/3] PCI: xilinx-cpm: Move interrupt bit definitions to common header [v6,1/3] PCI: xilinx-cpm: Move interrupt bit definitions to common header --- 2023-08-18 Havalige, Thippeswamy Superseded
[v4,3/3] PCI: xilinx-nwl: Increase ECAM size to accommodate 256 buses Untitled series #218681 --- 2023-08-14 Havalige, Thippeswamy Superseded
[v4,2/3] PCI: xilinx-nwl: Rename ECAM size default macro. Untitled series #218681 --- 2023-08-14 Havalige, Thippeswamy Superseded
[v3] PCI: xilinx-nwl: Remove unnecessary code which updates primary, secondary and sub-ordinate bus numbers [v3] PCI: xilinx-nwl: Remove unnecessary code which updates primary, secondary and sub-ordinate b... --- 2023-08-14 Havalige, Thippeswamy Superseded
[v1,2/2] dt-bindings: PCI: xilinx-nwl: Modify ECAM size in example. Fix ecam size value to discover 256 buses during --- 2023-08-07 Havalige, Thippeswamy Superseded
[v1,1/2] PCI: xilinx-nwl: Update ECAM default value and remove unnecessary code. Fix ecam size value to discover 256 buses during --- 2023-08-07 Havalige, Thippeswamy New
[V5,2/3] dt-bindings: PCI: xilinx-xdma: Add YAML schemas for Xilinx XDMA PCIe Root Port Bridge Add support for Xilinx XDMA Soft IP as Root Port. --- 2023-06-28 Havalige, Thippeswamy Superseded
[v4,3/3] PCI: xilinx-xdma: Add Xilinx XDMA Root Port driver [v4,1/3] Move and rename error interrupt bits to a common header. --- 2023-05-31 Havalige, Thippeswamy New
[v4,1/3] Move and rename error interrupt bits to a common header. [v4,1/3] Move and rename error interrupt bits to a common header. --- 2023-05-31 Havalige, Thippeswamy New
[v2,3/3] PCI: xilinx-xdma: Add Xilinx XDMA Root Port driver [v2,1/3] Move error interrupt bits to a common header. --- 2023-05-12 Havalige, Thippeswamy New
[v2,1/3] Move error interrupt bits to a common header. [v2,1/3] Move error interrupt bits to a common header. --- 2023-05-12 Havalige, Thippeswamy Superseded
[2/2] PCI: xilinx-xdma: Add Xilinx XDMA Root Port driver Add support for Xilinx XDMA Soft IP as Root Port. --- 2023-04-17 Havalige, Thippeswamy New
[1/2] dt-bindings: PCI: xilinx-xdma: Add YAML schemas for Xilinx XDMA PCIe Root Port Bridge Add support for Xilinx XDMA Soft IP as Root Port. --- 2023-04-17 Havalige, Thippeswamy Superseded
[v4,2/2] dt-bindings: PCI: xilinx-nwl: Convert to YAML schemas of Xilinx NWL PCIe Root Port Bridge Untitled series #191572 --- 2022-11-07 Havalige, Thippeswamy Accepted
[v2,1/2] dt-bindings: PCI: xilinx-pcie: Convert to YAML schemas of Xilinx AXI PCIe Root Port Bridge [v2,1/2] dt-bindings: PCI: xilinx-pcie: Convert to YAML schemas of Xilinx AXI PCIe Root Port Bridge --- 2022-11-01 Havalige, Thippeswamy Accepted
[12/13] microblaze/PCI: Remove support for Xilinx PCI host bridge Remove unused microblaze PCIe bus architecture --- 2022-10-25 Havalige, Thippeswamy Accepted
[09/13] microblaze/PCI: Remove unused pci_address_to_pio() conversion of CPU address to I/O port Remove unused microblaze PCIe bus architecture --- 2022-10-25 Havalige, Thippeswamy Accepted
[08/13] microblaze/PCI: Remove unused PCI Indirect ops Remove unused microblaze PCIe bus architecture --- 2022-10-25 Havalige, Thippeswamy Accepted
[06/13] microblaze/PCI: Remove unused allocation & free of PCI host bridge structure Remove unused microblaze PCIe bus architecture --- 2022-10-25 Havalige, Thippeswamy Accepted
[05/13] microblaze/PCI: Remove unused device tree parsing for a host bridge resources Remove unused microblaze PCIe bus architecture --- 2022-10-25 Havalige, Thippeswamy Accepted
[02/13] microblaze/PCI: Remove Null PCI config access unused functions Remove unused microblaze PCIe bus architecture --- 2022-10-25 Havalige, Thippeswamy Accepted
[1/2] dt-bindings: PCI: xilinx-pcie: Convert to YAML schemas of Xilinx AXI PCIe Root Port Bridge [1/2] dt-bindings: PCI: xilinx-pcie: Convert to YAML schemas of Xilinx AXI PCIe Root Port Bridge --- 2022-10-19 Havalige, Thippeswamy Superseded