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[50/50] pinctrl: renesas: checker: Add reserved field checks

Message ID f5a5159ba7b396e6f09dd3f23c864a74ed8e342d.1649865241.git.geert+renesas@glider.be
State Accepted
Commit fc883ed5a43e5f94894216896d74190ecf1356ff
Headers show
Series pinctrl: renesas: Reserved field optimizations | expand

Commit Message

Geert Uytterhoeven April 13, 2022, 5:24 p.m. UTC
Add checks for discovering registers with reserved fields that could
benefit from being described using variable-width reserved field
shorthands, reducing kernel size.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
 drivers/pinctrl/renesas/core.c | 11 ++++++++++-
 1 file changed, 10 insertions(+), 1 deletion(-)
diff mbox series

Patch

diff --git a/drivers/pinctrl/renesas/core.c b/drivers/pinctrl/renesas/core.c
index 356325df9c18f2ea..340835551466235f 100644
--- a/drivers/pinctrl/renesas/core.c
+++ b/drivers/pinctrl/renesas/core.c
@@ -878,7 +878,7 @@  static const struct sh_pfc_pin __init *sh_pfc_find_pin(
 static void __init sh_pfc_check_cfg_reg(const char *drvname,
 					const struct pinmux_cfg_reg *cfg_reg)
 {
-	unsigned int i, n, rw;
+	unsigned int i, n, rw, r;
 	int fw;
 
 	sh_pfc_check_reg(drvname, cfg_reg->reg,
@@ -887,6 +887,15 @@  static void __init sh_pfc_check_cfg_reg(const char *drvname,
 	if (cfg_reg->field_width) {
 		fw = cfg_reg->field_width;
 		n = (cfg_reg->reg_width / fw) << fw;
+		for (i = 0, r = 0; i < n; i += 1 << fw) {
+			if (is0s(&cfg_reg->enum_ids[i], 1 << fw))
+				r++;
+		}
+
+		if ((r << fw) * sizeof(u16) > cfg_reg->reg_width / fw)
+			sh_pfc_warn("reg 0x%x can be described with variable-width reserved fields\n",
+				    cfg_reg->reg);
+
 		/* Skip field checks (done at build time) */
 		goto check_enum_ids;
 	}