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bus: ti-sysc: fix reset sequencing
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| 3 patches
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andy.doan@linaro.org
andy.doan@linaro.org
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[3/3] bus: ti-sysc: avoid toggling power state of module during probe
bus: ti-sysc: fix reset sequencing
-
-
-
2019-10-07
Tero Kristo
New
[2/3] bus: ti-sysc: drop the extra hardreset during init
bus: ti-sysc: fix reset sequencing
-
-
-
2019-10-07
Tero Kristo
New
[1/3] bus: ti-sysc: re-order reset and main clock controls
bus: ti-sysc: fix reset sequencing
-
-
-
2019-10-07
Tero Kristo
New