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[0/8] MIPS: ingenic: Add support for the JZ4755 SoC

Message ID 20221009181338.2896660-1-lis8215@gmail.com
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Series MIPS: ingenic: Add support for the JZ4755 SoC | expand

Message

Siarhei Volkau Oct. 9, 2022, 6:13 p.m. UTC 
Add preliminary support for boards based on the JZ4755 SoC from
Ingenic.

It is a low-power SoC with a MIPS32r1 core running at ~432 MHz,
and has no FPU.

The JZ4755 SoC is supposed to be newer than the JZ4725B SoC, but its
internals are very close to each other. Also the Ingenic's kernel
source tree calls JZ4755 as JZ4750D and JZ4725B as JZ4750L, this might
mean that JZ4725B is a pin to pin compatible replacement for older
JZ4725 (both are LQFP128) but belongs to newer generation JZ475x. Who
knows?

I guess Ingenic released their SoCs in the following order:
 JZ4720  (MXU ?)
 JZ4725  (MXU ?)
 JZ4730  (MXU ?)
 JZ4740  (MXU1 r1)
 JZ4750  (MXU1 r2)
 JZ4755  (MXU1 r2)
 JZ4725b (MXU1 r2)
 JZ4760  ...

So JZ4755 DT is reusing many JZ4725B drivers because their support
in mainline kernel appears earlier.

Siarhei Volkau (8):
  dt-bindings: ingenic: Add support for the JZ4755 SoC
  MIPS: ingenic: add new machine type MACH_JZ4755
  dt-bindings: clock: Add Ingenic JZ4755 CGU header
  clk: Add Ingenic JZ4755 CGU driver
  pinctrl: ingenic: JZ4755 minor bug fixes
  dmaengine: JZ4780: Add support for the JZ4755.
  serial: 8250/ingenic: Add support for the JZ4750/JZ4755 SoCs
  MIPS: ingenic: Add support for the JZ4755 SoC

 .../bindings/clock/ingenic,cgu.yaml           |   2 +
 .../devicetree/bindings/dma/ingenic,dma.yaml  |   1 +
 .../bindings/serial/ingenic,uart.yaml         |   4 +
 arch/mips/boot/dts/ingenic/jz4755.dtsi        | 439 ++++++++++++++++++
 arch/mips/ingenic/Kconfig                     |   5 +
 drivers/clk/ingenic/Kconfig                   |  10 +
 drivers/clk/ingenic/Makefile                  |   1 +
 drivers/clk/ingenic/jz4755-cgu.c              | 350 ++++++++++++++
 drivers/dma/dma-jz4780.c                      |   8 +
 drivers/pinctrl/pinctrl-ingenic.c             |   4 +-
 drivers/tty/serial/8250/8250_ingenic.c        |  39 +-
 .../dt-bindings/clock/ingenic,jz4755-cgu.h    |  49 ++
 12 files changed, 905 insertions(+), 7 deletions(-)
 create mode 100644 arch/mips/boot/dts/ingenic/jz4755.dtsi
 create mode 100644 drivers/clk/ingenic/jz4755-cgu.c
 create mode 100644 include/dt-bindings/clock/ingenic,jz4755-cgu.h

Comments

Siarhei Volkau Oct. 10, 2022, 8:18 p.m. UTC | #1 
пн, 10 окт. 2022 г. в 17:55, Krzysztof Kozlowski
<krzysztof.kozlowski@linaro.org>:

> How do you plan to merge it? Usually these go via subsystem trees...

It's a new case for me, could you explain the problem a bit more?
What things should I bother with in the next patchset version?
Thanks in advance.
Greg Kroah-Hartman Oct. 10, 2022, 8:20 p.m. UTC | #2 
On Sun, Oct 09, 2022 at 09:13:36PM +0300, Siarhei Volkau wrote:
> These SoCs are close to others but they have a clock divisor /2 for low
> clock peripherals, thus to set up a proper baud rate we need to take
> this into account.
> 
> The divisor bit is located in CGU area, unfortunately the clk framework
> can't be used at early boot steps, so it's checked by direct readl()
> call.
> 
> Signed-off-by: Siarhei Volkau <lis8215@gmail.com>
> ---
>  drivers/tty/serial/8250/8250_ingenic.c | 39 ++++++++++++++++++++++----
>  1 file changed, 34 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/tty/serial/8250/8250_ingenic.c b/drivers/tty/serial/8250/8250_ingenic.c
> index 2b2f5d8d2..f2662720d 100644
> --- a/drivers/tty/serial/8250/8250_ingenic.c
> +++ b/drivers/tty/serial/8250/8250_ingenic.c
> @@ -70,7 +70,8 @@ static void ingenic_early_console_write(struct console *console,
>  			   ingenic_early_console_putc);
>  }
>  
> -static void __init ingenic_early_console_setup_clock(struct earlycon_device *dev)
> +static void __init ingenic_early_console_setup_clock(struct earlycon_device *dev,
> +						     int clkdiv)

What does "clkdiv" mean here?

And this function is rough, adding a random integer to a function
requires you to look it up every time you see this call.

If you only have 1 or 2 as an option, just have 2 functions instead
please.

thanks,

greg k-h
Krzysztof Kozlowski Oct. 11, 2022, 12:08 p.m. UTC | #3 
On 10/10/2022 16:18, Siarhei Volkau wrote:
> пн, 10 окт. 2022 г. в 17:55, Krzysztof Kozlowski
> <krzysztof.kozlowski@linaro.org>:
> 
>> How do you plan to merge it? Usually these go via subsystem trees...
> 
> It's a new case for me, could you explain the problem a bit more?
> What things should I bother with in the next patchset version?
> Thanks in advance.

Each binding goes via subsystem maintainer, not via DT bindings tree, so
keeping all in one patch messes with that.

Best regards,
Krzysztof
Siarhei Volkau Oct. 11, 2022, 6:38 p.m. UTC | #4 
пн, 10 окт. 2022 г. в 23:20, Greg Kroah-Hartman <gregkh@linuxfoundation.org>:
> What does "clkdiv" mean here?

That means a clock divisor between the input oscillator and UART
peripheral clock source. Most Ingenic SoCs don't have that divisor,
so 1 is always in effect for them.
However, the JZ4750 and JZ4755 have switchable /2 clock divisor.

> If you only have 1 or 2 as an option

Yes, it is.

> just have 2 functions instead please.

Got it, will do that.

Thank you.
Paul Cercueil Oct. 13, 2022, 9:03 a.m. UTC | #5 
Hi Siarhei,

Le lun., oct. 10 2022 at 23:18:05 +0300, Siarhei Volkau 
<lis8215@gmail.com> a écrit :
> пн, 10 окт. 2022 г. в 17:55, Krzysztof Kozlowski
> <krzysztof.kozlowski@linaro.org>:
> 
>>  How do you plan to merge it? Usually these go via subsystem trees...
> 
> It's a new case for me, could you explain the problem a bit more?
> What things should I bother with in the next patchset version?
> Thanks in advance.

Just split the patchset, most of your patches (e.g. DMA patch, CGU, 
pinctrl, UART) should be sent separately.

Otherwise it makes things much more complicated for merging.

Cheers,
-Paul