mbox series

[v5,00/17] tcg: CPUTLBEntryFull and TARGET_TB_PCREL

Message ID 20220925105124.82033-1-richard.henderson@linaro.org
Headers show
Series tcg: CPUTLBEntryFull and TARGET_TB_PCREL | expand

Message

Richard Henderson Sept. 25, 2022, 10:51 a.m. UTC 
Smooshing these two patch sets back together for review bandwidth.
I hope to make this the next tcg-next pull.

There are three from the first half, tlbentryfull, which are new.
These are following a hallway conversation with Peter about bits
in MemTxAttrs that are not actually related to memory transactions,
and infrastructure to address a to-do in an Arm patch set.

There are a few patches from the second half, pcrel, that have not
been reviewed. 

  07-target-sparc-Use-tlb_set_page_full.patch
  08-accel-tcg-Move-byte_swap-from-MemTxAttrs-to-CPUTL.patch
  09-accel-tcg-Add-force_aligned-to-CPUTLBEntryFull.patch
  10-accel-tcg-Remove-PageDesc-code_bitmap.patch
  13-accel-tcg-Do-not-align-tb-page_addr-0.patch
  15-accel-tcg-Introduce-tb_pc-and-tb_pc_log.patch
  16-accel-tcg-Introduce-TARGET_TB_PCREL.patch


r~


Richard Henderson (17):
  accel/tcg: Rename CPUIOTLBEntry to CPUTLBEntryFull
  accel/tcg: Drop addr member from SavedIOTLB
  accel/tcg: Suppress auto-invalidate in probe_access_internal
  accel/tcg: Introduce probe_access_full
  accel/tcg: Introduce tlb_set_page_full
  include/exec: Introduce TARGET_PAGE_ENTRY_EXTRA
  target/sparc: Use tlb_set_page_full
  accel/tcg: Move byte_swap from MemTxAttrs to CPUTLBEntryFull
  accel/tcg: Add force_aligned to CPUTLBEntryFull
  accel/tcg: Remove PageDesc code_bitmap
  accel/tcg: Use bool for page_find_alloc
  accel/tcg: Use DisasContextBase in plugin_gen_tb_start
  accel/tcg: Do not align tb->page_addr[0]
  include/hw/core: Create struct CPUJumpCache
  accel/tcg: Introduce tb_pc and tb_pc_log
  accel/tcg: Introduce TARGET_TB_PCREL
  accel/tcg: Split log_cpu_exec into inline and slow path

 include/exec/cpu-all.h                  |   6 +-
 include/exec/cpu-defs.h                 |  54 ++++--
 include/exec/exec-all.h                 |  84 ++++++++-
 include/exec/memattrs.h                 |   2 -
 include/exec/plugin-gen.h               |   7 +-
 include/hw/core/cpu.h                   |  10 +-
 accel/tcg/cpu-exec.c                    | 108 +++++++----
 accel/tcg/cputlb.c                      | 228 ++++++++++++++----------
 accel/tcg/plugin-gen.c                  |  22 +--
 accel/tcg/translate-all.c               | 168 ++++++-----------
 accel/tcg/translator.c                  |   2 +-
 target/arm/cpu.c                        |   4 +-
 target/arm/mte_helper.c                 |  14 +-
 target/arm/sve_helper.c                 |   4 +-
 target/arm/translate-a64.c              |   2 +-
 target/avr/cpu.c                        |   2 +-
 target/hexagon/cpu.c                    |   2 +-
 target/hppa/cpu.c                       |   4 +-
 target/i386/tcg/tcg-cpu.c               |   2 +-
 target/loongarch/cpu.c                  |   2 +-
 target/microblaze/cpu.c                 |   2 +-
 target/mips/tcg/exception.c             |   2 +-
 target/mips/tcg/sysemu/special_helper.c |   2 +-
 target/openrisc/cpu.c                   |   2 +-
 target/riscv/cpu.c                      |   4 +-
 target/rx/cpu.c                         |   2 +-
 target/s390x/tcg/mem_helper.c           |   4 -
 target/sh4/cpu.c                        |   4 +-
 target/sparc/cpu.c                      |   2 +-
 target/sparc/mmu_helper.c               | 123 ++++++-------
 target/tricore/cpu.c                    |   2 +-
 tcg/tcg.c                               |   6 +-
 32 files changed, 501 insertions(+), 381 deletions(-)

Comments

Richard Henderson Sept. 29, 2022, 2:16 a.m. UTC | #1 
On 9/25/22 03:51, Richard Henderson wrote:
> Smooshing these two patch sets back together for review bandwidth.
> I hope to make this the next tcg-next pull.
> 
> There are three from the first half, tlbentryfull, which are new.
> These are following a hallway conversation with Peter about bits
> in MemTxAttrs that are not actually related to memory transactions,
> and infrastructure to address a to-do in an Arm patch set.
> 
> There are a few patches from the second half, pcrel, that have not
> been reviewed.
> 
>    07-target-sparc-Use-tlb_set_page_full.patch
>    08-accel-tcg-Move-byte_swap-from-MemTxAttrs-to-CPUTL.patch
>    09-accel-tcg-Add-force_aligned-to-CPUTLBEntryFull.patch
>    10-accel-tcg-Remove-PageDesc-code_bitmap.patch
>    13-accel-tcg-Do-not-align-tb-page_addr-0.patch
>    15-accel-tcg-Introduce-tb_pc-and-tb_pc_log.patch
>    16-accel-tcg-Introduce-TARGET_TB_PCREL.patch

FWIW, the target/sparc patch fails (the peril of insufficiently tested airport updates), 
so I'm going to drop 7+8 until I have time to investigate.  I'm also going to drop patch 9 
for now, and present it alongside the Arm patch that will use it.

But otherwise, gentle ping.


r~
Mark Cave-Ayland Sept. 29, 2022, 6:53 a.m. UTC | #2 
On 29/09/2022 03:16, Richard Henderson wrote:

> On 9/25/22 03:51, Richard Henderson wrote:
>> Smooshing these two patch sets back together for review bandwidth.
>> I hope to make this the next tcg-next pull.
>>
>> There are three from the first half, tlbentryfull, which are new.
>> These are following a hallway conversation with Peter about bits
>> in MemTxAttrs that are not actually related to memory transactions,
>> and infrastructure to address a to-do in an Arm patch set.
>>
>> There are a few patches from the second half, pcrel, that have not
>> been reviewed.
>>
>>    07-target-sparc-Use-tlb_set_page_full.patch
>>    08-accel-tcg-Move-byte_swap-from-MemTxAttrs-to-CPUTL.patch
>>    09-accel-tcg-Add-force_aligned-to-CPUTLBEntryFull.patch
>>    10-accel-tcg-Remove-PageDesc-code_bitmap.patch
>>    13-accel-tcg-Do-not-align-tb-page_addr-0.patch
>>    15-accel-tcg-Introduce-tb_pc-and-tb_pc_log.patch
>>    16-accel-tcg-Introduce-TARGET_TB_PCREL.patch
> 
> FWIW, the target/sparc patch fails (the peril of insufficiently tested airport 
> updates), so I'm going to drop 7+8 until I have time to investigate.  I'm also going 
> to drop patch 9 for now, and present it alongside the Arm patch that will use it.

If it helps, the test case that exercises the IE (Invert Endian) page bit in 
target/sparc is Milax (OpenSolaris) which uses it to map PCI devices. Grab a suitable 
copy of milax032sparc.iso and test with:

     qemu-system-sparc64 -m 256 -cdrom milax032sparc.iso -nographic -boot d

You should see the IE pages accessed at the point where it starts poking the CDROM 
device, and timeouts if it isn't working.


ATB,

Mark.