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[v3,0/6] target/arm: Do memory alignment check for device memory

Message ID 20240301204110.656742-1-richard.henderson@linaro.org
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Series target/arm: Do memory alignment check for device memory | expand

Message

Richard Henderson March 1, 2024, 8:41 p.m. UTC 
v1: https://lore.kernel.org/qemu-devel/20230223204342.1093632-1-richard.henderson@linaro.org/
v2: https://lore.kernel.org/qemu-devel/20230621121902.1392277-1-richard.henderson@linaro.org/

Some of the v2 patch set was merged last June, but the rest languished.
No substantive changes from v2; only fixed rebase conflicts.


r~


Richard Henderson (6):
  target/arm: Support 32-byte alignment in pow2_align
  exec/memattrs: Remove target_tlb_bit*
  accel/tcg: Add tlb_fill_flags to CPUTLBEntryFull
  accel/tcg: Add TLB_CHECK_ALIGNED
  target/arm: Do memory type alignment check when translation disabled
  target/arm: Do memory type alignment check when translation enabled

 include/exec/cpu-all.h     |  4 +++-
 include/exec/memattrs.h    | 12 ------------
 include/hw/core/cpu.h      |  3 +++
 accel/tcg/cputlb.c         | 35 ++++++++++++++++++++++++++++-------
 target/arm/ptw.c           | 32 ++++++++++++++++++++++++++++++++
 target/arm/tcg/hflags.c    | 34 ++++++++++++++++++++++++++++++++--
 target/arm/tcg/translate.c |  8 +-------
 target/sparc/mmu_helper.c  |  2 +-
 8 files changed, 100 insertions(+), 30 deletions(-)

Comments

Peter Maydell March 4, 2024, 5:12 p.m. UTC | #1 
On Fri, 1 Mar 2024 at 20:42, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> v1: https://lore.kernel.org/qemu-devel/20230223204342.1093632-1-richard.henderson@linaro.org/
> v2: https://lore.kernel.org/qemu-devel/20230621121902.1392277-1-richard.henderson@linaro.org/
>
> Some of the v2 patch set was merged last June, but the rest languished.
> No substantive changes from v2; only fixed rebase conflicts.

Applied to target-arm.next (with the comment tweak to the last
patch as noted there), thanks.

-- PMM