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Show patches with
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| 8 patches
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andy.doan@linaro.org
andy.doan@linaro.org
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Patch
Series
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Date
Submitter
Delegate
State
[13/15] hw/riscv: sifive_u: Support different boot source per MSEL pin state
Untitled series #60036
-
-
-
2020-06-08
Bin Meng
New
[12/15] hw/riscv: sifive: Change SiFive E/U CPU reset vector to 0x1004
Untitled series #60036
-
-
-
2020-06-08
Bin Meng
New
[09/15] hw/riscv: sifive_u: Add reset functionality
Untitled series #60036
-
-
-
2020-06-08
Bin Meng
New
[07/15] hw/riscv: sifive_u: Hook a GPIO controller
Untitled series #60036
-
-
-
2020-06-08
Bin Meng
New
[06/15] hw/riscv: sifive_gpio: Add a new 'ngpio' property
Untitled series #60036
-
-
-
2020-06-08
Bin Meng
New
[04/15] hw/riscv: sifive_u: Generate device tree node for OTP
Untitled series #60036
-
-
-
2020-06-08
Bin Meng
New
[03/15] hw/riscv: sifive_u: Simplify the GEM IRQ connect code a little bit
Untitled series #60036
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-
-
2020-06-08
Bin Meng
New
[02/15] hw/riscv: opentitan: Remove the riscv_ prefix of the machine* and soc* functions
Untitled series #60036
-
-
-
2020-06-08
Bin Meng
New