Show patches with: Series = None       |    Archived = No       |   8 patches
Patch Series S/W/F Date Submitter Delegate State
[13/15] hw/riscv: sifive_u: Support different boot source per MSEL pin state Untitled series #60036 --- 2020-06-08 Bin Meng New
[12/15] hw/riscv: sifive: Change SiFive E/U CPU reset vector to 0x1004 Untitled series #60036 --- 2020-06-08 Bin Meng New
[09/15] hw/riscv: sifive_u: Add reset functionality Untitled series #60036 --- 2020-06-08 Bin Meng New
[07/15] hw/riscv: sifive_u: Hook a GPIO controller Untitled series #60036 --- 2020-06-08 Bin Meng New
[06/15] hw/riscv: sifive_gpio: Add a new 'ngpio' property Untitled series #60036 --- 2020-06-08 Bin Meng New
[04/15] hw/riscv: sifive_u: Generate device tree node for OTP Untitled series #60036 --- 2020-06-08 Bin Meng New
[03/15] hw/riscv: sifive_u: Simplify the GEM IRQ connect code a little bit Untitled series #60036 --- 2020-06-08 Bin Meng New
[02/15] hw/riscv: opentitan: Remove the riscv_ prefix of the machine* and soc* functions Untitled series #60036 --- 2020-06-08 Bin Meng New