Show patches with: Submitter = Anup Patel       |    State = Action Required       |    Archived = No       |   13 patches
Patch Series S/W/F Date Submitter Delegate State
[2/2] hw/riscv: virt: Allow passing custom DTB [1/2] hw/riscv: sifive_u: Allow passing custom DTB --- 2020-10-22 Anup Patel New
[1/2] hw/riscv: sifive_u: Allow passing custom DTB [1/2] hw/riscv: sifive_u: Allow passing custom DTB --- 2020-10-22 Anup Patel New
[3/3] target/riscv: Update MTINST/HTINST CSR in riscv_cpu_do_interrupt() [1/3] target/riscv: Optional feature to provide trapped instruction in CSRs --- 2020-07-29 Anup Patel New
[2/3] target/riscv: Fix write_htinst() implementation [1/3] target/riscv: Optional feature to provide trapped instruction in CSRs --- 2020-07-29 Anup Patel New
[1/3] target/riscv: Optional feature to provide trapped instruction in CSRs [1/3] target/riscv: Optional feature to provide trapped instruction in CSRs --- 2020-07-29 Anup Patel New
[v6,4/5] hw/riscv: spike: Allow creating multiple NUMA sockets RISC-V multi-socket support --- 2020-06-16 Anup Patel New
[v5,4/5] hw/riscv: spike: Allow creating multiple NUMA sockets [v5,1/5] hw/riscv: Allow creating multiple instances of CLINT --- 2020-05-29 Anup Patel New
[v4,4/4] hw/riscv: virt: Allow creating multiple NUMA sockets RISC-V multi-socket support --- 2020-05-28 Anup Patel New
[v3,3/4] hw/riscv: Allow creating multiple instances of PLIC [v3,1/4] hw/riscv: Allow creating multiple instances of CLINT --- 2020-05-27 Anup Patel New
[v2,2/5] hw/riscv: Allow creating multiple instances of CLINT RISC-V multi-socket support --- 2020-05-27 Anup Patel New
[v2,1/5] hw: Add sockets_specified field in CpuTopology RISC-V multi-socket support --- 2020-05-27 Anup Patel New
[2/4] hw/riscv: spike: Allow creating multiple sockets RISC-V multi-socket support --- 2020-05-16 Anup Patel New
[v3,3/3] hw/riscv/spike: Allow more than one CPUs RISC-V Spike machine improvements --- 2020-04-27 Anup Patel New