[v2,16/27] target/arm: Introduce arm_stage1_mmu_idx

Message ID	20181214052410.11863-17-richard.henderson@linaro.org
State	Superseded
Headers	show Delivered-To: patch@linaro.org Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; From: Richard Henderson <richard.henderson@linaro.org> To: qemu-devel@nongnu.org Date: Thu, 13 Dec 2018 23:23:59 -0600 Message-Id: <20181214052410.11863-17-richard.henderson@linaro.org> In-Reply-To: <20181214052410.11863-1-richard.henderson@linaro.org> References: <20181214052410.11863-1-richard.henderson@linaro.org> Subject: [Qemu-devel] [PATCH v2 16/27] target/arm: Introduce arm_stage1_mmu_idx Precedence: list Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" <qemu-devel-bounces+patch=linaro.org@nongnu.org>
Series	target/arm: Implement ARMv8.3-PAuth \| expand [v2,00/27] target/arm: Implement ARMv8.3-PAuth [v2,01/27] target/arm: Add state for the ARMv8.3-PAuth extension [v2,02/27] target/arm: Add SCTLR bits through ARMv8.5 [v2,03/27] target/arm: Add PAuth active bit to tbflags [v2,04/27] target/arm: Add PAuth helpers [v2,05/27] target/arm: Decode PAuth within system hint space [v2,06/27] target/arm: Rearrange decode in disas_data_proc_1src [v2,07/27] target/arm: Decode PAuth within disas_data_proc_1src [v2,08/27] target/arm: Decode PAuth within disas_data_proc_2src [v2,09/27] target/arm: Move helper_exception_return to helper-a64.c [v2,10/27] target/arm: Add new_pc argument to helper_exception_return [v2,11/27] target/arm: Rearrange decode in disas_uncond_b_reg [v2,12/27] target/arm: Decode PAuth within disas_uncond_b_reg [v2,13/27] target/arm: Decode Load/store register (pac) [v2,14/27] target/arm: Move cpu_mmu_index out of line [v2,15/27] target/arm: Introduce arm_mmu_idx [v2,16/27] target/arm: Introduce arm_stage1_mmu_idx [v2,17/27] target/arm: Create ARMVAParameters and helpers [v2,18/27] target/arm: Reuse aa64_va_parameters for setting tbflags [v2,19/27] target/arm: Export aa64_va_parameters to internals.h [v2,20/27] target/arm: Implement pauth_strip [v2,21/27] target/arm: Implement pauth_auth [v2,22/27] target/arm: Implement pauth_addpac [v2,23/27] target/arm: Implement pauth_computepac [v2,24/27] target/arm: Add PAuth system registers [v2,25/27] target/arm: Enable PAuth for -cpu max [v2,26/27] target/arm: Enable PAuth for user-only, part 2 [v2,27/27] target/arm: Tidy TBI handling in gen_a64_set_pc

Message ID

20181214052410.11863-17-richard.henderson@linaro.org

State

Superseded

Headers

Received-SPF: pass (google.com: domain of
	qemu-devel-bounces+patch=linaro.org@nongnu.org designates
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	client-ip=2001:4830:134:3::11; 
From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Date: Thu, 13 Dec 2018 23:23:59 -0600
Message-Id: <20181214052410.11863-17-richard.henderson@linaro.org>
In-Reply-To: <20181214052410.11863-1-richard.henderson@linaro.org>
References: <20181214052410.11863-1-richard.henderson@linaro.org>
Subject: [Qemu-devel] [PATCH v2 16/27] target/arm: Introduce
	arm_stage1_mmu_idx
Precedence: list
Cc: peter.maydell@linaro.org
Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org
Sender: "Qemu-devel" <qemu-devel-bounces+patch=linaro.org@nongnu.org>

Series

target/arm: Implement ARMv8.3-PAuth | expand

Commit Message

Richard Henderson Dec. 14, 2018, 5:23 a.m. UTC

While we could expose stage_1_mmu_idx, the combination is
probably going to be more useful.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

---
 target/arm/internals.h | 15 +++++++++++++++
 target/arm/helper.c    |  7 +++++++
 2 files changed, 22 insertions(+)

-- 
2.17.2

Comments

Peter Maydell Jan. 4, 2019, 6:58 p.m. UTC | #1

On Fri, 14 Dec 2018 at 05:24, Richard Henderson
<richard.henderson@linaro.org> wrote:
>

> While we could expose stage_1_mmu_idx, the combination is

> probably going to be more useful.

>

> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


Reviewed-by: Peter Maydell <peter.maydell@linaro.org>


thanks
-- PMM

diff --git a/target/arm/internals.h b/target/arm/internals.h
index 4a52fe58b6..1d0d0392c9 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -920,4 +920,19 @@  void arm_cpu_update_vfiq(ARMCPU *cpu);
  */
 ARMMMUIdx arm_mmu_idx(CPUARMState *env);
 
+/**
+ * arm_stage1_mmu_idx:
+ * @env: The cpu environment
+ *
+ * Return the ARMMMUIdx for the stage1 traversal for the current regime.
+ */
+#ifdef CONFIG_USER_ONLY
+static inline ARMMMUIdx arm_stage1_mmu_idx(CPUARMState *env)
+{
+    return ARMMMUIdx_S1NSE0;
+}
+#else
+ARMMMUIdx arm_stage1_mmu_idx(CPUARMState *env);
+#endif
+
 #endif
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 50c1db16dd..b1c0ff923f 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -12998,6 +12998,13 @@  int cpu_mmu_index(CPUARMState *env, bool ifetch)
     return arm_to_core_mmu_idx(arm_mmu_idx(env));
 }
 
+#ifndef CONFIG_USER_ONLY
+ARMMMUIdx arm_stage1_mmu_idx(CPUARMState *env)
+{
+    return stage_1_mmu_idx(arm_mmu_idx(env));
+}
+#endif
+
 void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
                           target_ulong *cs_base, uint32_t *pflags)
 {

[v2,16/27] target/arm: Introduce arm_stage1_mmu_idx

Commit Message

Comments

Patch