Show patches with: none      |   75790 patches
« 1 2 ... 51 52 53 … 757 758 »
Patch Series S/W/F Date Submitter Delegate State
[11/12] plugins: remove non per_vcpu inline operation from API TCG Plugin inline operation enhancement --- 2024-01-11 Pierrick Bouvier New
[10/12] contrib/plugins/howvec: migrate to new per_vcpu API TCG Plugin inline operation enhancement --- 2024-01-11 Pierrick Bouvier New
[09/12] contrib/plugins/hotblocks: migrate to new per_vcpu API TCG Plugin inline operation enhancement --- 2024-01-11 Pierrick Bouvier New
[08/12] tests/plugin/bb: migrate to new per_vcpu API TCG Plugin inline operation enhancement --- 2024-01-11 Pierrick Bouvier New
[07/12] tests/plugin/insn: migrate to new per_vcpu API TCG Plugin inline operation enhancement --- 2024-01-11 Pierrick Bouvier New
[06/12] tests/plugin/mem: migrate to new per_vcpu API TCG Plugin inline operation enhancement --- 2024-01-11 Pierrick Bouvier New
[05/12] tests/plugin/mem: fix race condition with callbacks TCG Plugin inline operation enhancement --- 2024-01-11 Pierrick Bouvier New
[04/12] tests/plugin/inline: migrate to new per_vcpu API TCG Plugin inline operation enhancement --- 2024-01-11 Pierrick Bouvier New
[03/12] tests/plugin: add test plugin for inline operations TCG Plugin inline operation enhancement --- 2024-01-11 Pierrick Bouvier New
[02/12] plugins: add inline operation per vcpu TCG Plugin inline operation enhancement --- 2024-01-11 Pierrick Bouvier New
[01/12] plugins: implement inline operation with cpu_index offset TCG Plugin inline operation enhancement --- 2024-01-11 Pierrick Bouvier Superseded
.gitlab-ci.d/buildtest.yml: Work around htags bug when environment is large .gitlab-ci.d/buildtest.yml: Work around htags bug when environment is large --- 2024-01-11 Peter Maydell Superseded
[5/5] target/riscv: Rename tcg_cpu_FOO() to include 'riscv' misc: Trivial code rename cleanup --- 2024-01-11 Philippe Mathieu-Daudé Superseded
[4/5] target/i386: Rename tcg_cpu_FOO() to include 'x86' misc: Trivial code rename cleanup --- 2024-01-11 Philippe Mathieu-Daudé Superseded
[3/5] hw/s390x: Rename cpu_class_init() to include 'sclp' misc: Trivial code rename cleanup --- 2024-01-11 Philippe Mathieu-Daudé Superseded
[2/5] hw/core/cpu: Rename cpu_class_init() to include 'common' misc: Trivial code rename cleanup --- 2024-01-11 Philippe Mathieu-Daudé Superseded
[1/5] accel: Rename accel_init_ops_interfaces() to include 'system' misc: Trivial code rename cleanup --- 2024-01-11 Philippe Mathieu-Daudé Superseded
[PULL,41/41] target/arm: Add FEAT_NV2 to max, neoverse-n2, neoverse-v1 CPUs [PULL,01/41] hw/arm: add cache controller for Freescale i.MX6 --- 2024-01-11 Peter Maydell Accepted
[PULL,40/41] target/arm: Enhance CPU_LOG_INT to show SPSR on AArch64 exception-entry [PULL,01/41] hw/arm: add cache controller for Freescale i.MX6 --- 2024-01-11 Peter Maydell Accepted
[PULL,39/41] target/arm: Report HCR_EL2.{NV,NV1,NV2} in cpu dumps [PULL,01/41] hw/arm: add cache controller for Freescale i.MX6 --- 2024-01-11 Peter Maydell Accepted
[PULL,38/41] hw/intc/arm_gicv3_cpuif: Mark up VNCR offsets for GIC CPU registers [PULL,01/41] hw/arm: add cache controller for Freescale i.MX6 --- 2024-01-11 Peter Maydell Accepted
[PULL,37/41] target/arm: Mark up VNCR offsets (offsets >= 0x200, except GIC) [PULL,01/41] hw/arm: add cache controller for Freescale i.MX6 --- 2024-01-11 Peter Maydell Accepted
[PULL,36/41] target/arm: Mark up VNCR offsets (offsets 0x168..0x1f8) [PULL,01/41] hw/arm: add cache controller for Freescale i.MX6 --- 2024-01-11 Peter Maydell Accepted
[PULL,35/41] target/arm: Mark up VNCR offsets (offsets 0x100..0x160) [PULL,01/41] hw/arm: add cache controller for Freescale i.MX6 --- 2024-01-11 Peter Maydell Accepted
[PULL,34/41] target/arm: Mark up VNCR offsets (offsets 0x0..0xff) [PULL,01/41] hw/arm: add cache controller for Freescale i.MX6 --- 2024-01-11 Peter Maydell Accepted
[PULL,33/41] target/arm: Report VNCR_EL2 based faults correctly [PULL,01/41] hw/arm: add cache controller for Freescale i.MX6 --- 2024-01-11 Peter Maydell Accepted
[PULL,32/41] target/arm: Implement FEAT_NV2 redirection of sysregs to RAM [PULL,01/41] hw/arm: add cache controller for Freescale i.MX6 --- 2024-01-11 Peter Maydell Not Applicable
[PULL,31/41] target/arm: Handle FEAT_NV2 redirection of SPSR_EL2, ELR_EL2, ESR_EL2, FAR_EL2 [PULL,01/41] hw/arm: add cache controller for Freescale i.MX6 --- 2024-01-11 Peter Maydell Not Applicable
[PULL,30/41] target/arm: Handle FEAT_NV2 changes to when SPSR_EL1.M reports EL2 [PULL,01/41] hw/arm: add cache controller for Freescale i.MX6 --- 2024-01-11 Peter Maydell Accepted
[PULL,29/41] target/arm: Implement VNCR_EL2 register [PULL,01/41] hw/arm: add cache controller for Freescale i.MX6 --- 2024-01-11 Peter Maydell Accepted
[PULL,28/41] target/arm: Handle HCR_EL2 accesses for FEAT_NV2 bits [PULL,01/41] hw/arm: add cache controller for Freescale i.MX6 --- 2024-01-11 Peter Maydell Accepted
[PULL,27/41] target/arm: Add FEAT_NV to max, neoverse-n2, neoverse-v1 CPUs [PULL,01/41] hw/arm: add cache controller for Freescale i.MX6 --- 2024-01-11 Peter Maydell Accepted
[PULL,26/41] target/arm: Handle FEAT_NV page table attribute changes [PULL,01/41] hw/arm: add cache controller for Freescale i.MX6 --- 2024-01-11 Peter Maydell Accepted
[PULL,25/41] target/arm: Treat LDTR* and STTR* as LDR/STR when NV, NV1 is 1, 1 [PULL,01/41] hw/arm: add cache controller for Freescale i.MX6 --- 2024-01-11 Peter Maydell Accepted
[PULL,24/41] target/arm: Don't honour PSTATE.PAN when HCR_EL2.{NV, NV1} == {1, 1} [PULL,01/41] hw/arm: add cache controller for Freescale i.MX6 --- 2024-01-11 Peter Maydell Not Applicable
[PULL,23/41] target/arm: Always use arm_pan_enabled() when checking if PAN is enabled [PULL,01/41] hw/arm: add cache controller for Freescale i.MX6 --- 2024-01-11 Peter Maydell Accepted
[PULL,22/41] target/arm: Trap registers when HCR_EL2.{NV, NV1} == {1, 1} [PULL,01/41] hw/arm: add cache controller for Freescale i.MX6 --- 2024-01-11 Peter Maydell Accepted
[PULL,21/41] target/arm: Set SPSR_EL1.M correctly when nested virt is enabled [PULL,01/41] hw/arm: add cache controller for Freescale i.MX6 --- 2024-01-11 Peter Maydell Accepted
[PULL,20/41] target/arm: Make NV reads of CurrentEL return EL2 [PULL,01/41] hw/arm: add cache controller for Freescale i.MX6 --- 2024-01-11 Peter Maydell Accepted
[PULL,19/41] target/arm: Trap sysreg accesses for FEAT_NV [PULL,01/41] hw/arm: add cache controller for Freescale i.MX6 --- 2024-01-11 Peter Maydell Not Applicable
[PULL,18/41] target/arm: Move FPU/SVE/SME access checks up above ARM_CP_SPECIAL_MASK check [PULL,01/41] hw/arm: add cache controller for Freescale i.MX6 --- 2024-01-11 Peter Maydell Accepted
[PULL,17/41] target/arm: Make EL2 cpreg accessfns safe for FEAT_NV EL1 accesses [PULL,01/41] hw/arm: add cache controller for Freescale i.MX6 --- 2024-01-11 Peter Maydell Accepted
[PULL,16/41] target/arm: *_EL12 registers should UNDEF when HCR_EL2.E2H is 0 [PULL,01/41] hw/arm: add cache controller for Freescale i.MX6 --- 2024-01-11 Peter Maydell Accepted
[PULL,15/41] target/arm: Record correct opcode fields in cpreg for E2H aliases [PULL,01/41] hw/arm: add cache controller for Freescale i.MX6 --- 2024-01-11 Peter Maydell Accepted
[PULL,14/41] target/arm: Allow use of upper 32 bits of TBFLAG_A64 [PULL,01/41] hw/arm: add cache controller for Freescale i.MX6 --- 2024-01-11 Peter Maydell Accepted
[PULL,13/41] target/arm: Always honour HCR_EL2.TSC when HCR_EL2.NV is set [PULL,01/41] hw/arm: add cache controller for Freescale i.MX6 --- 2024-01-11 Peter Maydell Accepted
[PULL,12/41] target/arm: Enable trapping of ERET for FEAT_NV [PULL,01/41] hw/arm: add cache controller for Freescale i.MX6 --- 2024-01-11 Peter Maydell Not Applicable
[PULL,11/41] target/arm: Implement HCR_EL2.AT handling [PULL,01/41] hw/arm: add cache controller for Freescale i.MX6 --- 2024-01-11 Peter Maydell Accepted
[PULL,10/41] target/arm: Handle HCR_EL2 accesses for bits introduced with FEAT_NV [PULL,01/41] hw/arm: add cache controller for Freescale i.MX6 --- 2024-01-11 Peter Maydell Accepted
[PULL,09/41] hw/intc/arm_gicv3_cpuif: handle LPIs in in the list registers [PULL,01/41] hw/arm: add cache controller for Freescale i.MX6 --- 2024-01-11 Peter Maydell Accepted
[PULL,08/41] target/arm: Set CTR_EL0.{IDC,DIC} for the 'max' CPU [PULL,01/41] hw/arm: add cache controller for Freescale i.MX6 --- 2024-01-11 Peter Maydell Accepted
[PULL,07/41] hw/arm: Add missing QOM parent for v7-M SoCs [PULL,01/41] hw/arm: add cache controller for Freescale i.MX6 --- 2024-01-11 Peter Maydell Accepted
[PULL,06/41] hw/arm/socs: configure priority bits for existing SOCs [PULL,01/41] hw/arm: add cache controller for Freescale i.MX6 --- 2024-01-11 Peter Maydell Accepted
[PULL,05/41] hw/arm/armv7m: alias the NVIC "num-prio-bits" property [PULL,01/41] hw/arm: add cache controller for Freescale i.MX6 --- 2024-01-11 Peter Maydell Not Applicable
[PULL,04/41] hw/intc/armv7m_nvic: add "num-prio-bits" property [PULL,01/41] hw/arm: add cache controller for Freescale i.MX6 --- 2024-01-11 Peter Maydell Accepted
[PULL,03/41] hw/arm: Add minimal support for the B-L475E-IOT01A board [PULL,01/41] hw/arm: add cache controller for Freescale i.MX6 --- 2024-01-11 Peter Maydell Not Applicable
[PULL,02/41] hw/arm: Add minimal support for the STM32L4x5 SoC [PULL,01/41] hw/arm: add cache controller for Freescale i.MX6 --- 2024-01-11 Peter Maydell Not Applicable
[PULL,01/41] hw/arm: add cache controller for Freescale i.MX6 [PULL,01/41] hw/arm: add cache controller for Freescale i.MX6 --- 2024-01-11 Peter Maydell Not Applicable
[PULL,00/41] target-arm queue --- 2024-01-11 Peter Maydell Not Applicable
hw/core: Handle cpu_model_from_type() returning NULL value hw/core: Handle cpu_model_from_type() returning NULL value --- 2024-01-11 Philippe Mathieu-Daudé New
[v3,38/38] tcg/tci: Support TCG_COND_TST{EQ,NE} tcg: Introduce TCG_COND_TST{EQ,NE} --- 2024-01-10 Richard Henderson Superseded
[v3,37/38] tcg/s390x: Support TCG_COND_TST{EQ,NE} tcg: Introduce TCG_COND_TST{EQ,NE} --- 2024-01-10 Richard Henderson Superseded
[v3,36/38] tcg/s390x: Add TCG_CT_CONST_CMP tcg: Introduce TCG_COND_TST{EQ,NE} --- 2024-01-10 Richard Henderson Superseded
[v3,35/38] tcg/s390x: Split constraint A into J+U tcg: Introduce TCG_COND_TST{EQ,NE} --- 2024-01-10 Richard Henderson Superseded
[v3,34/38] tcg/ppc: Support TCG_COND_TST{EQ,NE} tcg: Introduce TCG_COND_TST{EQ,NE} --- 2024-01-10 Richard Henderson Superseded
[v3,33/38] tcg/ppc: Add TCG_CT_CONST_CMP tcg: Introduce TCG_COND_TST{EQ,NE} --- 2024-01-10 Richard Henderson Superseded
[v3,32/38] tcg/ppc: Tidy up tcg_target_const_match tcg: Introduce TCG_COND_TST{EQ,NE} --- 2024-01-10 Richard Henderson Superseded
[v3,31/38] tcg/ppc: Use cr0 in tcg_to_bc and tcg_to_isel tcg: Introduce TCG_COND_TST{EQ,NE} --- 2024-01-10 Richard Henderson Superseded
[v3,30/38] tcg/ppc: Sink tcg_to_bc usage into tcg_out_bc tcg: Introduce TCG_COND_TST{EQ,NE} --- 2024-01-10 Richard Henderson Superseded
[v3,29/38] tcg/sparc64: Support TCG_COND_TST{EQ,NE} tcg: Introduce TCG_COND_TST{EQ,NE} --- 2024-01-10 Richard Henderson Superseded
[v3,28/38] tcg/sparc64: Pass TCGCond to tcg_out_cmp tcg: Introduce TCG_COND_TST{EQ,NE} --- 2024-01-10 Richard Henderson Superseded
[v3,27/38] tcg/sparc64: Hoist read of tcg_cond_to_rcond tcg: Introduce TCG_COND_TST{EQ,NE} --- 2024-01-10 Richard Henderson Superseded
[v3,26/38] tcg/i386: Use TEST r,r to test 8/16/32 bits tcg: Introduce TCG_COND_TST{EQ,NE} --- 2024-01-10 Richard Henderson Superseded
[v3,25/38] tcg/i386: Improve TSTNE/TESTEQ vs powers of two tcg: Introduce TCG_COND_TST{EQ,NE} --- 2024-01-10 Richard Henderson Superseded
[v3,24/38] tcg/i386: Support TCG_COND_TST{EQ,NE} tcg: Introduce TCG_COND_TST{EQ,NE} --- 2024-01-10 Richard Henderson Superseded
[v3,23/38] tcg/i386: Move tcg_cond_to_jcc[] into tcg_out_cmp tcg: Introduce TCG_COND_TST{EQ,NE} --- 2024-01-10 Richard Henderson Superseded
[v3,22/38] tcg/i386: Pass x86 condition codes to tcg_out_cmov tcg: Introduce TCG_COND_TST{EQ,NE} --- 2024-01-10 Richard Henderson Superseded
[v3,21/38] tcg/arm: Support TCG_COND_TST{EQ,NE} tcg: Introduce TCG_COND_TST{EQ,NE} --- 2024-01-10 Richard Henderson Superseded
[v3,20/38] tcg/arm: Factor tcg_out_cmp() out tcg: Introduce TCG_COND_TST{EQ,NE} --- 2024-01-10 Richard Henderson Superseded
[v3,19/38] tcg/aarch64: Generate CBNZ for TSTNE of UINT32_MAX tcg: Introduce TCG_COND_TST{EQ,NE} --- 2024-01-10 Richard Henderson New
[v3,18/38] tcg/aarch64: Generate TBZ, TBNZ tcg: Introduce TCG_COND_TST{EQ,NE} --- 2024-01-10 Richard Henderson New
[v3,17/38] tcg/aarch64: Support TCG_COND_TST{EQ,NE} tcg: Introduce TCG_COND_TST{EQ,NE} --- 2024-01-10 Richard Henderson Superseded
[v3,16/38] tcg: Add TCGConst argument to tcg_target_const_match tcg: Introduce TCG_COND_TST{EQ,NE} --- 2024-01-10 Richard Henderson Superseded
[v3,15/38] target/s390x: Improve general case of disas_jcc tcg: Introduce TCG_COND_TST{EQ,NE} --- 2024-01-10 Richard Henderson Superseded
[v3,14/38] target/s390x: Use TCG_COND_TSTNE for CC_OP_{TM,ICM} tcg: Introduce TCG_COND_TST{EQ,NE} --- 2024-01-10 Richard Henderson Superseded
[v3,13/38] target/sparc: Use TCG_COND_TSTEQ in gen_op_mulscc tcg: Introduce TCG_COND_TST{EQ,NE} --- 2024-01-10 Richard Henderson New
[v3,12/38] target/m68k: Use TCG_COND_TST{EQ, NE} in gen_fcc_cond tcg: Introduce TCG_COND_TST{EQ,NE} --- 2024-01-10 Richard Henderson Superseded
[v3,11/38] target/alpha: Use TCG_COND_TSTNE for gen_fold_mzero tcg: Introduce TCG_COND_TST{EQ,NE} --- 2024-01-10 Richard Henderson Superseded
[v3,10/38] target/alpha: Use TCG_COND_TST{EQ, NE} for CMOVLB{C, S} tcg: Introduce TCG_COND_TST{EQ,NE} --- 2024-01-10 Richard Henderson Superseded
[v3,09/38] target/alpha: Use TCG_COND_TST{EQ,NE} for BLB{C,S} tcg: Introduce TCG_COND_TST{EQ,NE} --- 2024-01-10 Richard Henderson Superseded
[v3,08/38] target/alpha: Pass immediate value to gen_bcond_internal() tcg: Introduce TCG_COND_TST{EQ,NE} --- 2024-01-10 Richard Henderson Superseded
[v3,07/38] tcg/optimize: Lower TCG_COND_TST{EQ, NE} if unsupported tcg: Introduce TCG_COND_TST{EQ,NE} --- 2024-01-10 Richard Henderson Superseded
[v3,06/38] tcg/optimize: Handle TCG_COND_TST{EQ,NE} tcg: Introduce TCG_COND_TST{EQ,NE} --- 2024-01-10 Richard Henderson Superseded
[v3,05/38] tcg/optimize: Do swap_commutative2 in do_constant_folding_cond2 tcg: Introduce TCG_COND_TST{EQ,NE} --- 2024-01-10 Richard Henderson Superseded
[v3,04/38] tcg/optimize: Split out do_constant_folding_cond1 tcg: Introduce TCG_COND_TST{EQ,NE} --- 2024-01-10 Richard Henderson Superseded
[v3,03/38] tcg/optimize: Split out arg_is_const_val tcg: Introduce TCG_COND_TST{EQ,NE} --- 2024-01-10 Richard Henderson Superseded
[v3,02/38] tcg: Introduce TCG_TARGET_HAS_tst tcg: Introduce TCG_COND_TST{EQ,NE} --- 2024-01-10 Richard Henderson Superseded
[v3,01/38] tcg: Introduce TCG_COND_TST{EQ,NE} tcg: Introduce TCG_COND_TST{EQ,NE} --- 2024-01-10 Richard Henderson New
[PULL,4/4] util: fix build with musl libc on ppc64le [PULL,1/4] tcg/i386: convert add/sub of 128 to sub/add of -128 --- 2024-01-10 Richard Henderson Accepted
[PULL,3/4] tcg/ppc: Use new registers for LQ destination [PULL,1/4] tcg/i386: convert add/sub of 128 to sub/add of -128 --- 2024-01-10 Richard Henderson New
« 1 2 ... 51 52 53 … 757 758 »