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[v4,29/69] target/arm: Diagnose writeback register in list for LDM for v7

Message ID 20190904193059.26202-30-richard.henderson@linaro.org
State Accepted
Commit 3949f4675d13c587078f8f423845a3a537a22595
Headers show
Series target/arm: Convert aa32 base isa to decodetree | expand

Commit Message

Richard Henderson Sept. 4, 2019, 7:30 p.m. UTC 
Prior to v7, for the A32 encoding, this operation wrote an UNKNOWN
value back to the base register.  Starting in v7 this is UNPREDICTABLE.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

---
 target/arm/translate.c | 9 +++++++++
 1 file changed, 9 insertions(+)

-- 
2.17.1
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Patch

diff --git a/target/arm/translate.c b/target/arm/translate.c
index 1f3c7bbd54..b67e7389d3 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -9997,6 +9997,15 @@  static bool do_ldm(DisasContext *s, arg_ldst_block *a)
 
 static bool trans_LDM_a32(DisasContext *s, arg_ldst_block *a)
 {
+    /*
+     * Writeback register in register list is UNPREDICTABLE
+     * for ArchVersion() >= 7.  Prior to v7, A32 would write
+     * an UNKNOWN value to the base register.
+     */
+    if (ENABLE_ARCH_7 && a->w && (a->list & (1 << a->rn))) {
+        unallocated_encoding(s);
+        return true;
+    }
     return do_ldm(s, a);
 }