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[27/36] target/arm: Convert Neon VABA 3-reg-same to decodetree

Message ID 20200430181003.21682-28-peter.maydell@linaro.org
State Superseded
Headers show
Series target/arm: Convert Neon to decodetree (part 1) | expand

Commit Message

Peter Maydell April 30, 2020, 6:09 p.m. UTC 
Convert the NEON VABA insn in the 3-reg-same group to decodetree.
This is the only insn in this group which does an integer
accumulate into the destination register.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

---
 target/arm/translate-neon.inc.c | 76 +++++++++++++++++++++++++++++++++
 target/arm/translate.c          |  7 +--
 target/arm/neon-dp.decode       |  3 ++
 3 files changed, 80 insertions(+), 6 deletions(-)

-- 
2.20.1

Comments

Richard Henderson May 1, 2020, 2:29 a.m. UTC | #1 
On 4/30/20 11:09 AM, Peter Maydell wrote:
> +    for (pass = 0; pass < (a->q ? 4 : 2); pass++) {

> +        tmp = neon_load_reg(a->vn, pass);

> +        tmp2 = neon_load_reg(a->vm, pass);

> +        abd_fn(tmp, tmp, tmp2);

> +        tcg_temp_free_i32(tmp2);

> +        tmp2 = neon_load_reg(a->vd, pass);

> +        add_fn(tmp, tmp, tmp2);

> +        tcg_temp_free_i32(tmp2);

> +        neon_store_reg(a->vd, pass, tmp);

> +    }

> +    return true;

> +}

> +

> +static bool trans_VABA_S_3s(DisasContext *s, arg_3same *a)

> +{

> +    static NeonGenTwoOpFn * const abd_fns[] = {

> +        gen_helper_neon_abd_s8,

> +        gen_helper_neon_abd_s16,

> +        gen_helper_neon_abd_s32,

> +    };

> +    static NeonGenTwoOpFn * const add_fns[] = {

> +        gen_helper_neon_add_u8,

> +        gen_helper_neon_add_u16,

> +        tcg_gen_add_i32,

> +    };


This can be packaged into one operation.  E.g.

static void gen_aba_s8(TCGv_i32 d, TCGv_i32 n, TCGv_i32 m)
{
    TCGv_i32 t = tcg_temp_new_i32();

    gen_helper_neon_abd_s8(t, n, m);
    gen_helper_neon_add_u8(d, d, t);
    tcg_temp_free_i32(t);gen_aba_s8
}

static const GVecGen3 op = {
    .fni4 = gen_aba_s8,
    .load_dest = true
};

etc.

FWIW, this is one that I've fully converted on my sve2 branch.  aba(n,m,a) =
max(n,m) - min(n,m) + a -- four fully vectorized operations.  So anything that
allows a drop-in replacement would be nice.  But whatever is easiest for you.


r~
diff mbox series

Patch

diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c
index 084c78eea58..4692448fc5f 100644
--- a/target/arm/translate-neon.inc.c
+++ b/target/arm/translate-neon.inc.c
@@ -1128,3 +1128,79 @@  DO_3SAME_QS32(VQRSHL_U,qrshl_u)
 
 DO_3SAME_SHIFT32(VRSHL_S, rshl_s)
 DO_3SAME_SHIFT32(VRSHL_U, rshl_u)
+
+static bool do_vaba(DisasContext *s, arg_3same *a,
+                    NeonGenTwoOpFn *abd_fn, NeonGenTwoOpFn *add_fn)
+{
+    /* VABA: handled elementwise 32 bits at a time, accumulating */
+    TCGv_i32 tmp, tmp2;
+    int pass;
+
+    if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
+        return false;
+    }
+
+    /* UNDEF accesses to D16-D31 if they don't exist. */
+    if (!dc_isar_feature(aa32_simd_r32, s) &&
+        ((a->vd | a->vn | a->vm) & 0x10)) {
+        return false;
+    }
+
+    if ((a->vn | a->vm | a->vd) & a->q) {
+        return false;
+    }
+
+    if (!vfp_access_check(s)) {
+        return true;
+    }
+
+    for (pass = 0; pass < (a->q ? 4 : 2); pass++) {
+        tmp = neon_load_reg(a->vn, pass);
+        tmp2 = neon_load_reg(a->vm, pass);
+        abd_fn(tmp, tmp, tmp2);
+        tcg_temp_free_i32(tmp2);
+        tmp2 = neon_load_reg(a->vd, pass);
+        add_fn(tmp, tmp, tmp2);
+        tcg_temp_free_i32(tmp2);
+        neon_store_reg(a->vd, pass, tmp);
+    }
+    return true;
+}
+
+static bool trans_VABA_S_3s(DisasContext *s, arg_3same *a)
+{
+    static NeonGenTwoOpFn * const abd_fns[] = {
+        gen_helper_neon_abd_s8,
+        gen_helper_neon_abd_s16,
+        gen_helper_neon_abd_s32,
+    };
+    static NeonGenTwoOpFn * const add_fns[] = {
+        gen_helper_neon_add_u8,
+        gen_helper_neon_add_u16,
+        tcg_gen_add_i32,
+    };
+
+    if (a->size > 2) {
+        return false;
+    }
+    return do_vaba(s, a, abd_fns[a->size], add_fns[a->size]);
+}
+
+static bool trans_VABA_U_3s(DisasContext *s, arg_3same *a)
+{
+    static NeonGenTwoOpFn * const abd_fns[] = {
+        gen_helper_neon_abd_u8,
+        gen_helper_neon_abd_u16,
+        gen_helper_neon_abd_u32,
+    };
+    static NeonGenTwoOpFn * const add_fns[] = {
+        gen_helper_neon_add_u8,
+        gen_helper_neon_add_u16,
+        tcg_gen_add_i32,
+    };
+
+    if (a->size > 2) {
+        return false;
+    }
+    return do_vaba(s, a, abd_fns[a->size], add_fns[a->size]);
+}
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 4406fe54647..b04643cec9a 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -4793,6 +4793,7 @@  static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
         case NEON_3R_VQSHL:
         case NEON_3R_VRSHL:
         case NEON_3R_VQRSHL:
+        case NEON_3R_VABA:
             /* Already handled by decodetree */
             return 1;
         }
@@ -4862,12 +4863,6 @@  static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
             tmp2 = neon_load_reg(rm, pass);
         }
         switch (op) {
-        case NEON_3R_VABA:
-            GEN_NEON_INTEGER_OP(abd);
-            tcg_temp_free_i32(tmp2);
-            tmp2 = neon_load_reg(rd, pass);
-            gen_neon_add(size, tmp, tmp2);
-            break;
         case NEON_3R_VPMAX:
             GEN_NEON_INTEGER_OP(pmax);
             break;
diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode
index ae442071ef1..d91f944f84a 100644
--- a/target/arm/neon-dp.decode
+++ b/target/arm/neon-dp.decode
@@ -113,6 +113,9 @@  VMIN_U_3s        1111 001 1 0 . .. .... .... 0110 . . . 1 .... @3same
 VABD_S_3s        1111 001 0 0 . .. .... .... 0111 . . . 0 .... @3same
 VABD_U_3s        1111 001 1 0 . .. .... .... 0111 . . . 0 .... @3same
 
+VABA_S_3s        1111 001 0 0 . .. .... .... 0111 . . . 1 .... @3same
+VABA_U_3s        1111 001 1 0 . .. .... .... 0111 . . . 1 .... @3same
+
 VADD_3s          1111 001 0 0 . .. .... .... 1000 . . . 0 .... @3same
 VSUB_3s          1111 001 1 0 . .. .... .... 1000 . . . 0 .... @3same