diff mbox series

[31/36] target/arm: Convert Neon VADD, VSUB, VABD 3-reg-same insns to decodetree

Message ID 20200430181003.21682-32-peter.maydell@linaro.org
State Superseded
Headers show
Series target/arm: Convert Neon to decodetree (part 1) | expand

Commit Message

Peter Maydell April 30, 2020, 6:09 p.m. UTC 
Convert the Neon VADD, VSUB, VABD 3-reg-same insns to decodetree.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

---
 target/arm/translate-neon.inc.c | 54 +++++++++++++++++++++++++++++++++
 target/arm/translate.c          | 10 ++----
 target/arm/neon-dp.decode       |  8 +++++
 3 files changed, 65 insertions(+), 7 deletions(-)

-- 
2.20.1

Comments

Richard Henderson May 1, 2020, 3:57 a.m. UTC | #1 
On 4/30/20 11:09 AM, Peter Maydell wrote:
> +    TCGv_ptr fpstatus = get_fpstatus_ptr(1);

> +    for (pass = 0; pass < (a->q ? 4 : 2); pass++) {

> +        tmp = neon_load_reg(a->vn, pass);

> +        tmp2 = neon_load_reg(a->vm, pass);

> +        fn(tmp, tmp, tmp2, fpstatus);

> +        tcg_temp_free_i32(tmp2);

> +        neon_store_reg(a->vd, pass, tmp);

> +    }

> +    tcg_temp_free_ptr(fpstatus);

> +    return true;

> +}

> +

> +/*

> + * For all the functions using this macro, size == 1 means fp16,

> + * which is an architecture extension we don't implement yet.

> + */

> +#define DO_3S_FP(INSN,FUNC)                                         \

> +    static bool trans_##INSN##_fp_3s(DisasContext *s, arg_3same *a) \

> +    {                                                               \

> +        if (a->size != 0) {                                         \

> +            /* TODO fp16 support */                                 \

> +            return false;                                           \

> +        }                                                           \

> +        return do_3same_fp(s, a, FUNC);                             \

> +    }


We already have helper_gvec_fadd_s and helper_fsub_s to handle the whole vector
with one call.  Use with tcg_gen_gvec_3_ptr, with the status pointer as the 4th
argument.

Interestingly, I can't find the current use of this helper.  I must have been
starting on that translation but got stopped?  There's no current full-vector
helper for abd_f32, but it would take very few lines to add it.


r~
diff mbox series

Patch

diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c
index 2fab547840d..6a27b7673c2 100644
--- a/target/arm/translate-neon.inc.c
+++ b/target/arm/translate-neon.inc.c
@@ -1321,3 +1321,57 @@  static bool trans_VQRDMULH_3s(DisasContext *s, arg_3same *a)
     }
     return do_3same_32(s, a, fns[a->size - 1]);
 }
+
+static bool do_3same_fp(DisasContext *s, arg_3same *a, VFPGen3OpSPFn *fn)
+{
+    /* FP operations handled elementwise 32 bits at a time */
+    TCGv_i32 tmp, tmp2;
+    int pass;
+
+    if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
+        return false;
+    }
+
+    /* UNDEF accesses to D16-D31 if they don't exist. */
+    if (!dc_isar_feature(aa32_simd_r32, s) &&
+        ((a->vd | a->vn | a->vm) & 0x10)) {
+        return false;
+    }
+
+    if ((a->vn | a->vm | a->vd) & a->q) {
+        return false;
+    }
+
+    if (!vfp_access_check(s)) {
+        return true;
+    }
+
+    TCGv_ptr fpstatus = get_fpstatus_ptr(1);
+    for (pass = 0; pass < (a->q ? 4 : 2); pass++) {
+        tmp = neon_load_reg(a->vn, pass);
+        tmp2 = neon_load_reg(a->vm, pass);
+        fn(tmp, tmp, tmp2, fpstatus);
+        tcg_temp_free_i32(tmp2);
+        neon_store_reg(a->vd, pass, tmp);
+    }
+    tcg_temp_free_ptr(fpstatus);
+    return true;
+}
+
+/*
+ * For all the functions using this macro, size == 1 means fp16,
+ * which is an architecture extension we don't implement yet.
+ */
+#define DO_3S_FP(INSN,FUNC)                                         \
+    static bool trans_##INSN##_fp_3s(DisasContext *s, arg_3same *a) \
+    {                                                               \
+        if (a->size != 0) {                                         \
+            /* TODO fp16 support */                                 \
+            return false;                                           \
+        }                                                           \
+        return do_3same_fp(s, a, FUNC);                             \
+    }
+
+DO_3S_FP(VADD, gen_helper_vfp_adds)
+DO_3S_FP(VSUB, gen_helper_vfp_subs)
+DO_3S_FP(VABD, gen_helper_neon_abd_f32)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 9fec1889613..c944cbf20af 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -4797,6 +4797,9 @@  static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
         switch (op) {
         case NEON_3R_FLOAT_ARITH:
             pairwise = (u && size < 2); /* if VPADD (float) */
+            if (!pairwise) {
+                return 1; /* handled by decodetree */
+            }
             break;
         case NEON_3R_FLOAT_MINMAX:
             pairwise = u; /* if VPMIN/VPMAX (float) */
@@ -4853,16 +4856,9 @@  static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
         {
             TCGv_ptr fpstatus = get_fpstatus_ptr(1);
             switch ((u << 2) | size) {
-            case 0: /* VADD */
             case 4: /* VPADD */
                 gen_helper_vfp_adds(tmp, tmp, tmp2, fpstatus);
                 break;
-            case 2: /* VSUB */
-                gen_helper_vfp_subs(tmp, tmp, tmp2, fpstatus);
-                break;
-            case 6: /* VABD */
-                gen_helper_neon_abd_f32(tmp, tmp, tmp2, fpstatus);
-                break;
             default:
                 abort();
             }
diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode
index 8ceedd8b8d8..9d6a17d6f04 100644
--- a/target/arm/neon-dp.decode
+++ b/target/arm/neon-dp.decode
@@ -45,6 +45,10 @@ 
 @3same_q0        .... ... . . . size:2 .... .... .... . 0 . . .... \
                  &3same vm=%vm_dp vn=%vn_dp vd=%vd_dp q=0
 
+# For FP insns the high bit of 'size' is used as part of opcode decode
+@3same_fp        .... ... . . . . size:1 .... .... .... . q:1 . . .... \
+                 &3same vm=%vm_dp vn=%vn_dp vd=%vd_dp
+
 VHADD_S_3s       1111 001 0 0 . .. .... .... 0000 . . . 0 .... @3same
 VHADD_U_3s       1111 001 1 0 . .. .... .... 0000 . . . 0 .... @3same
 VQADD_S_3s       1111 001 0 0 . .. .... .... 0000 . . . 1 .... @3same
@@ -154,3 +158,7 @@  SHA256SU1_3s     1111 001 1 0 . 10 .... .... 1100 . 1 . 0 .... \
                  vm=%vm_dp vn=%vn_dp vd=%vd_dp
 
 VQRDMLSH_3s      1111 001 1 0 . .. .... .... 1100 ... 1 .... @3same
+
+VADD_fp_3s       1111 001 0 0 . 0 . .... .... 1101 ... 0 .... @3same_fp
+VSUB_fp_3s       1111 001 0 0 . 1 . .... .... 1101 ... 0 .... @3same_fp
+VABD_fp_3s       1111 001 1 0 . 1 . .... .... 1101 ... 0 .... @3same_fp