Show patches with: Series = target/riscv: support vector extension v0.7.1       |    State = Action Required       |    Archived = No       |   15 patches
Patch Series S/W/F Date Submitter Delegate State
[v9,60/61] target/riscv: vector compress instruction target/riscv: support vector extension v0.7.1 --- 2020-06-10 LIU Zhiwei New
[v9,55/61] target/riscv: integer extract instruction target/riscv: support vector extension v0.7.1 --- 2020-06-10 LIU Zhiwei New
[v9,53/61] target/riscv: vector iota instruction target/riscv: support vector extension v0.7.1 --- 2020-06-10 LIU Zhiwei New
[v9,52/61] target/riscv: set-X-first mask bit target/riscv: support vector extension v0.7.1 --- 2020-06-10 LIU Zhiwei New
[v9,49/61] target/riscv: vector mask-register logical instructions target/riscv: support vector extension v0.7.1 --- 2020-06-10 LIU Zhiwei New
[v9,47/61] target/riscv: vector single-width floating-point reduction instructions target/riscv: support vector extension v0.7.1 --- 2020-06-10 LIU Zhiwei New
[v9,46/61] target/riscv: vector wideing integer reduction instructions target/riscv: support vector extension v0.7.1 --- 2020-06-10 LIU Zhiwei New
[v9,42/61] target/riscv: vector floating-point/integer type-convert instructions target/riscv: support vector extension v0.7.1 --- 2020-06-10 LIU Zhiwei New
[v9,40/61] target/riscv: vector floating-point classify instructions target/riscv: support vector extension v0.7.1 --- 2020-06-10 LIU Zhiwei New
[v9,32/61] target/riscv: vector single-width floating-point multiply/divide instructions target/riscv: support vector extension v0.7.1 --- 2020-06-10 LIU Zhiwei New
[v9,28/61] target/riscv: vector single-width scaling shift instructions target/riscv: support vector extension v0.7.1 --- 2020-06-10 LIU Zhiwei New
[v9,24/61] target/riscv: vector single-width saturating add and subtract target/riscv: support vector extension v0.7.1 --- 2020-06-10 LIU Zhiwei New
[v9,15/61] target/riscv: vector narrowing integer right shift instructions target/riscv: support vector extension v0.7.1 --- 2020-06-10 LIU Zhiwei New
[v9,13/61] target/riscv: vector bitwise logical instructions target/riscv: support vector extension v0.7.1 --- 2020-06-10 LIU Zhiwei New
[v9,01/61] target/riscv: add vector extension field in CPURISCVState target/riscv: support vector extension v0.7.1 --- 2020-06-10 LIU Zhiwei New