Patch Metrics

Linaro contributions to qemu-devel.

Patches per month: Submitted Accepted

Project Details

List addressqemu-devel@nongnu.org
Source treehttp://git.qemu.org/git/qemu.git
Last commit scanned1ea06abceec61b6f3ab33dadb0510b6e09fb61e2
Show patches with: Submitter = LIU Zhiwei       |    State = Action Required       |    Archived = No       |   85 patches
Patch Series S/W/F Date Submitter Delegate State
[2/3] fpu/softfloat: Define convert operations for bfloat16 Implement blfoat16 in softfloat 0 0 0 2020-08-13 LIU Zhiwei New
[2/2] target/riscv: fix vector index load/store constraints Untitled series #58837 0 0 0 2020-07-21 LIU Zhiwei New
[RFC,7/8] fpu/softfloat: define covert operation for bfloat16 Implement blfoat16 in softfloat 0 0 0 2020-07-12 LIU Zhiwei New
[RFC,6/8] fpu/softfloat: define operation for bfloat16 Implement blfoat16 in softfloat 0 0 0 2020-07-12 LIU Zhiwei New
[RFC,4/8] fpu/softfloat: add pack and unpack interfaces for bfloat16 Implement blfoat16 in softfloat 0 0 0 2020-07-12 LIU Zhiwei New
[RFC,3/8] fpu/softfloat: add FloatFmt for bfloat16 Implement blfoat16 in softfloat 0 0 0 2020-07-12 LIU Zhiwei New
[11/11] riscv: Add configure script Untitled series #59037 0 0 0 2020-07-11 LIU Zhiwei New
[10/11] riscv: Implement payload load interfaces Untitled series #59037 0 0 0 2020-07-11 LIU Zhiwei New
[09/11] riscv: Define riscv struct reginfo Untitled series #59037 0 0 0 2020-07-11 LIU Zhiwei New
[04/11] riscv: Add RV64F instructions description Untitled series #59037 0 0 0 2020-07-11 LIU Zhiwei New
[02/11] riscv: Add RV64M instructions description Untitled series #59037 0 0 0 2020-07-11 LIU Zhiwei New
[1/1] tcg/tcg-op: nonatomic_op should work with smaller memop [1/1] tcg/tcg-op: nonatomic_op should work with smaller memop 0 0 0 2020-07-01 LIU Zhiwei New
[1/2] tcg/tcg-op: Fix nonatomic_op load with MO_SIGN [1/2] tcg/tcg-op: Fix nonatomic_op load with MO_SIGN 0 0 0 2020-06-29 LIU Zhiwei New
[6/6] target/riscv: clean up fmv.w.x target/riscv: NaN-boxing for multiple precison 0 0 0 2020-06-26 LIU Zhiwei New
[4/6] target/riscv: check before allocating TCG temps target/riscv: NaN-boxing for multiple precison 0 0 0 2020-06-26 LIU Zhiwei New
[2/6] target/riscv: NaN-boxing compute, sign-injection and convert instructions. target/riscv: NaN-boxing for multiple precison 0 0 0 2020-06-26 LIU Zhiwei New
[v11,58/61] target/riscv: vector slide instructions target/riscv: support vector extension v0.7.1 0 0 0 2020-06-23 LIU Zhiwei New
[v11,38/61] target/riscv: vector floating-point sign-injection instructions target/riscv: support vector extension v0.7.1 0 0 0 2020-06-23 LIU Zhiwei New
[v11,36/61] target/riscv: vector floating-point square-root instruction target/riscv: support vector extension v0.7.1 0 0 0 2020-06-23 LIU Zhiwei New
[v11,34/61] target/riscv: vector single-width floating-point fused multiply-add instructions target/riscv: support vector extension v0.7.1 0 0 0 2020-06-23 LIU Zhiwei New
[v11,16/61] target/riscv: vector integer comparison instructions target/riscv: support vector extension v0.7.1 0 0 0 2020-06-23 LIU Zhiwei New
[v11,08/61] target/riscv: add fault-only-first unit stride load target/riscv: support vector extension v0.7.1 0 0 0 2020-06-23 LIU Zhiwei New
[v10,57/61] target/riscv: floating-point scalar move instructions target/riscv: support vector extension v0.7.1 0 0 0 2020-06-20 LIU Zhiwei New
[v10,43/61] target/riscv: widening floating-point/integer type-convert instructions target/riscv: support vector extension v0.7.1 0 0 0 2020-06-20 LIU Zhiwei New
[v10,41/61] target/riscv: vector floating-point merge instructions target/riscv: support vector extension v0.7.1 0 0 0 2020-06-20 LIU Zhiwei New
[v10,21/61] target/riscv: vector single-width integer multiply-add instructions target/riscv: support vector extension v0.7.1 0 0 0 2020-06-20 LIU Zhiwei New
[v10,29/61] target/riscv: vector narrowing fixed-point clip instructions [v10,01/61] target/riscv: add vector extension field in CPURISCVState 0 0 0 2020-06-20 LIU Zhiwei New
[v10,20/61] target/riscv: vector widening integer multiply instructions [v10,01/61] target/riscv: add vector extension field in CPURISCVState 0 0 0 2020-06-20 LIU Zhiwei New
[v10,17/61] target/riscv: vector integer min/max instructions [v10,01/61] target/riscv: add vector extension field in CPURISCVState 0 0 0 2020-06-20 LIU Zhiwei New
[v10,10/61] target/riscv: vector single-width integer add and subtract [v10,01/61] target/riscv: add vector extension field in CPURISCVState 0 0 0 2020-06-20 LIU Zhiwei New
[v10,07/61] target/riscv: add vector index load and store instructions [v10,01/61] target/riscv: add vector extension field in CPURISCVState 0 0 0 2020-06-20 LIU Zhiwei New
[v9,60/61] target/riscv: vector compress instruction target/riscv: support vector extension v0.7.1 0 0 0 2020-06-10 LIU Zhiwei New
[v9,55/61] target/riscv: integer extract instruction target/riscv: support vector extension v0.7.1 0 0 0 2020-06-10 LIU Zhiwei New
[v9,53/61] target/riscv: vector iota instruction target/riscv: support vector extension v0.7.1 0 0 0 2020-06-10 LIU Zhiwei New
[v9,52/61] target/riscv: set-X-first mask bit target/riscv: support vector extension v0.7.1 0 0 0 2020-06-10 LIU Zhiwei New
[v9,49/61] target/riscv: vector mask-register logical instructions target/riscv: support vector extension v0.7.1 0 0 0 2020-06-10 LIU Zhiwei New
[v9,47/61] target/riscv: vector single-width floating-point reduction instructions target/riscv: support vector extension v0.7.1 0 0 0 2020-06-10 LIU Zhiwei New
[v9,46/61] target/riscv: vector wideing integer reduction instructions target/riscv: support vector extension v0.7.1 0 0 0 2020-06-10 LIU Zhiwei New
[v9,42/61] target/riscv: vector floating-point/integer type-convert instructions target/riscv: support vector extension v0.7.1 0 0 0 2020-06-10 LIU Zhiwei New
[v9,40/61] target/riscv: vector floating-point classify instructions target/riscv: support vector extension v0.7.1 0 0 0 2020-06-10 LIU Zhiwei New
[v9,32/61] target/riscv: vector single-width floating-point multiply/divide instructions target/riscv: support vector extension v0.7.1 0 0 0 2020-06-10 LIU Zhiwei New
[v9,28/61] target/riscv: vector single-width scaling shift instructions target/riscv: support vector extension v0.7.1 0 0 0 2020-06-10 LIU Zhiwei New
[v9,24/61] target/riscv: vector single-width saturating add and subtract target/riscv: support vector extension v0.7.1 0 0 0 2020-06-10 LIU Zhiwei New
[v9,15/61] target/riscv: vector narrowing integer right shift instructions target/riscv: support vector extension v0.7.1 0 0 0 2020-06-10 LIU Zhiwei New
[v9,13/61] target/riscv: vector bitwise logical instructions target/riscv: support vector extension v0.7.1 0 0 0 2020-06-10 LIU Zhiwei New
[v9,01/61] target/riscv: add vector extension field in CPURISCVState target/riscv: support vector extension v0.7.1 0 0 0 2020-06-10 LIU Zhiwei New
[v8,62/62] target/riscv: configure and turn on vector extension from command line target/riscv: support vector extension v0.7.1 0 0 0 2020-05-21 LIU Zhiwei New
[v8,60/62] target/riscv: vector register gather instruction target/riscv: support vector extension v0.7.1 0 0 0 2020-05-21 LIU Zhiwei New
[v8,58/62] target/riscv: floating-point scalar move instructions target/riscv: support vector extension v0.7.1 0 0 0 2020-05-21 LIU Zhiwei New
[v8,57/62] target/riscv: integer scalar move instruction target/riscv: support vector extension v0.7.1 0 0 0 2020-05-21 LIU Zhiwei New
[v8,55/62] target/riscv: vector element index instruction target/riscv: support vector extension v0.7.1 0 0 0 2020-05-21 LIU Zhiwei New
[v8,52/62] target/riscv: vmfirst find-first-set mask bit target/riscv: support vector extension v0.7.1 0 0 0 2020-05-21 LIU Zhiwei New
[v8,51/62] target/riscv: vector mask population count vmpopc target/riscv: support vector extension v0.7.1 0 0 0 2020-05-21 LIU Zhiwei New
[v8,49/62] target/riscv: vector widening floating-point reduction instructions target/riscv: support vector extension v0.7.1 0 0 0 2020-05-21 LIU Zhiwei New
[v8,46/62] target/riscv: vector single-width integer reduction instructions target/riscv: support vector extension v0.7.1 0 0 0 2020-05-21 LIU Zhiwei New
[v8,45/62] target/riscv: narrowing floating-point/integer type-convert instructions target/riscv: support vector extension v0.7.1 0 0 0 2020-05-21 LIU Zhiwei New
[v8,40/62] target/riscv: vector floating-point compare instructions target/riscv: support vector extension v0.7.1 0 0 0 2020-05-21 LIU Zhiwei New
[v8,38/62] target/riscv: vector floating-point min/max instructions target/riscv: support vector extension v0.7.1 0 0 0 2020-05-21 LIU Zhiwei New
[v8,36/62] target/riscv: vector widening floating-point fused multiply-add instructions target/riscv: support vector extension v0.7.1 0 0 0 2020-05-21 LIU Zhiwei New
[v8,34/62] target/riscv: vector widening floating-point multiply target/riscv: support vector extension v0.7.1 0 0 0 2020-05-21 LIU Zhiwei New
[v8,32/62] target/riscv: vector widening floating-point add/subtract instructions target/riscv: support vector extension v0.7.1 0 0 0 2020-05-21 LIU Zhiwei New
[v8,30/62] target/riscv: Update fp_status when float rounding mode changes target/riscv: support vector extension v0.7.1 0 0 0 2020-05-21 LIU Zhiwei New
[v8,29/62] target/riscv: vector narrowing fixed-point clip instructions target/riscv: support vector extension v0.7.1 0 0 0 2020-05-21 LIU Zhiwei New
[v8,27/62] target/riscv: vector widening saturating scaled multiply-add target/riscv: support vector extension v0.7.1 0 0 0 2020-05-21 LIU Zhiwei New
[v8,26/62] target/riscv: vector single-width fractional multiply with rounding and saturation target/riscv: support vector extension v0.7.1 0 0 0 2020-05-21 LIU Zhiwei New
[v8,25/62] target/riscv: vector single-width averaging add and subtract target/riscv: support vector extension v0.7.1 0 0 0 2020-05-21 LIU Zhiwei New
[v8,23/62] target/riscv: vector integer merge and move instructions target/riscv: support vector extension v0.7.1 0 0 0 2020-05-21 LIU Zhiwei New
[v8,22/62] target/riscv: vector widening integer multiply-add instructions target/riscv: support vector extension v0.7.1 0 0 0 2020-05-21 LIU Zhiwei New
[v8,21/62] target/riscv: vector single-width integer multiply-add instructions target/riscv: support vector extension v0.7.1 0 0 0 2020-05-21 LIU Zhiwei New
[v8,19/62] target/riscv: vector integer divide instructions target/riscv: support vector extension v0.7.1 0 0 0 2020-05-21 LIU Zhiwei New
[v8,18/62] target/riscv: vector single-width integer multiply instructions target/riscv: support vector extension v0.7.1 0 0 0 2020-05-21 LIU Zhiwei New
[v8,17/62] target/riscv: vector integer min/max instructions target/riscv: support vector extension v0.7.1 0 0 0 2020-05-21 LIU Zhiwei New
[v8,14/62] target/riscv: vector single-width bit shift instructions target/riscv: support vector extension v0.7.1 0 0 0 2020-05-21 LIU Zhiwei New
[v8,12/62] target/riscv: vector integer add-with-carry / subtract-with-borrow instructions target/riscv: support vector extension v0.7.1 0 0 0 2020-05-21 LIU Zhiwei New
[v8,11/62] target/riscv: vector widening integer add and subtract target/riscv: support vector extension v0.7.1 0 0 0 2020-05-21 LIU Zhiwei New
[v8,09/62] target/riscv: add vector amo operations target/riscv: support vector extension v0.7.1 0 0 0 2020-05-21 LIU Zhiwei New
[v8,06/62] target/riscv: add vector stride load and store instructions target/riscv: support vector extension v0.7.1 0 0 0 2020-05-21 LIU Zhiwei New
[v8,05/62] target/riscv: add an internals.h header target/riscv: support vector extension v0.7.1 0 0 0 2020-05-21 LIU Zhiwei New
[v8,04/62] target/riscv: add vector configure instruction target/riscv: support vector extension v0.7.1 0 0 0 2020-05-21 LIU Zhiwei New
[v8,03/62] target/riscv: support vector extension csr target/riscv: support vector extension v0.7.1 0 0 0 2020-05-21 LIU Zhiwei New
[v8,02/62] target/riscv: implementation-defined constant parameters target/riscv: support vector extension v0.7.1 0 0 0 2020-05-21 LIU Zhiwei New
[RFC,6/8] riscv: Add configure script RISCV risu porting 0 0 0 2020-04-30 LIU Zhiwei New
[RFC,5/8] riscv: Add standard test case RISCV risu porting 0 0 0 2020-04-30 LIU Zhiwei New
[RFC,2/8] riscv: Generate payload scripts RISCV risu porting 0 0 0 2020-04-30 LIU Zhiwei New
[RFC,1/8] riscv: Add RV64I instructions description RISCV risu porting 0 0 0 2020-04-30 LIU Zhiwei New