Show patches with: Submitter = Bin Meng       |   104 patches
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Patch Series S/W/F Date Submitter Delegate State
[v3] hw/riscv: microchip_pfsoc: Correct DDR memory map [v3] hw/riscv: microchip_pfsoc: Correct DDR memory map --- 2020-11-01 Bin Meng New
hw/9pfs: virtio-9p: Ensure config space is a multiple of 4 bytes hw/9pfs: virtio-9p: Ensure config space is a multiple of 4 bytes --- 2020-10-29 Bin Meng New
[v2,10/10] hw/riscv: microchip_pfsoc: Hook the I2C1 controller hw/riscv: microchip_pfsoc: Support factory HSS boot out of the box --- 2020-10-28 Bin Meng Superseded
[v2,09/10] hw/riscv: microchip_pfsoc: Correct DDR memory map hw/riscv: microchip_pfsoc: Support factory HSS boot out of the box --- 2020-10-28 Bin Meng Superseded
[v2,08/10] hw/riscv: microchip_pfsoc: Map the reserved memory at address 0 hw/riscv: microchip_pfsoc: Support factory HSS boot out of the box --- 2020-10-28 Bin Meng New
[v2,07/10] hw/riscv: microchip_pfsoc: Connect the SYSREG module hw/riscv: microchip_pfsoc: Support factory HSS boot out of the box --- 2020-10-28 Bin Meng Superseded
[v2,06/10] hw/misc: Add Microchip PolarFire SoC SYSREG module support hw/riscv: microchip_pfsoc: Support factory HSS boot out of the box --- 2020-10-28 Bin Meng Superseded
[v2,05/10] hw/riscv: microchip_pfsoc: Connect the IOSCB module hw/riscv: microchip_pfsoc: Support factory HSS boot out of the box --- 2020-10-28 Bin Meng New
[v2,04/10] hw/misc: Add Microchip PolarFire SoC IOSCB module support hw/riscv: microchip_pfsoc: Support factory HSS boot out of the box --- 2020-10-28 Bin Meng Superseded
[v2,03/10] hw/riscv: microchip_pfsoc: Connect DDR memory controller modules hw/riscv: microchip_pfsoc: Support factory HSS boot out of the box --- 2020-10-28 Bin Meng Superseded
[v2,02/10] hw/misc: Add Microchip PolarFire SoC DDR Memory Controller support hw/riscv: microchip_pfsoc: Support factory HSS boot out of the box --- 2020-10-28 Bin Meng Superseded
[v2,01/10] hw/riscv: microchip_pfsoc: Document where to look at the SoC memory maps hw/riscv: microchip_pfsoc: Support factory HSS boot out of the box --- 2020-10-28 Bin Meng New
[RESEND,9/9] hw/riscv: microchip_pfsoc: Hook the I2C1 controller hw/riscv: microchip_pfsoc: Support factory HSS boot out of the box --- 2020-10-27 Bin Meng New
[RESEND,8/9] hw/riscv: microchip_pfsoc: Correct DDR memory map hw/riscv: microchip_pfsoc: Support factory HSS boot out of the box --- 2020-10-27 Bin Meng Superseded
[RESEND,7/9] hw/riscv: microchip_pfsoc: Map debug memory hw/riscv: microchip_pfsoc: Support factory HSS boot out of the box --- 2020-10-27 Bin Meng New
[RESEND,6/9] hw/riscv: microchip_pfsoc: Connect the SYSREG module hw/riscv: microchip_pfsoc: Support factory HSS boot out of the box --- 2020-10-27 Bin Meng New
[RESEND,5/9] hw/misc: Add Microchip PolarFire SoC SYSREG module support hw/riscv: microchip_pfsoc: Support factory HSS boot out of the box --- 2020-10-27 Bin Meng New
[RESEND,4/9] hw/riscv: microchip_pfsoc: Connect the IOSCB module hw/riscv: microchip_pfsoc: Support factory HSS boot out of the box --- 2020-10-27 Bin Meng Superseded
[RESEND,3/9] hw/misc: Add Microchip PolarFire SoC IOSCB module support hw/riscv: microchip_pfsoc: Support factory HSS boot out of the box --- 2020-10-27 Bin Meng New
[RESEND,2/9] hw/riscv: microchip_pfsoc: Connect DDR memory controller modules Untitled series #73562 --- 2020-10-27 Bin Meng New
[RESEND,1/9] hw/misc: Add Microchip PolarFire SoC DDR Memory Controller support hw/riscv: microchip_pfsoc: Support factory HSS boot out of the box --- 2020-10-27 Bin Meng Superseded
[2/9] hw/riscv: microchip_pfsoc: Connect DDR memory controller modules hw/riscv: microchip_pfsoc: Support factory HSS boot out of the box --- 2020-10-27 Bin Meng Superseded
[1/9] hw/misc: Add Microchip PolarFire SoC DDR Memory Controller support hw/riscv: microchip_pfsoc: Support factory HSS boot out of the box --- 2020-10-27 Bin Meng New
hw/sd: Fix 2 GiB card CSD register values hw/sd: Fix 2 GiB card CSD register values --- 2020-10-25 Bin Meng New
hw/sd: Zero out function selection fields before being populated hw/sd: Zero out function selection fields before being populated --- 2020-10-24 Bin Meng New
target/i386: seg_helper: Correct segement selector nullification in the RET/IRET helper target/i386: seg_helper: Correct segement selector nullification in the RET/IRET helper --- 2020-10-22 Bin Meng New
[RESEND,v2] hw/intc: Move sifive_plic.h to the include directory [RESEND,v2] hw/intc: Move sifive_plic.h to the include directory --- 2020-10-13 Bin Meng Superseded
[v2] hw/intc: Move sifive_plic.h to the include directory [v2] hw/intc: Move sifive_plic.h to the include directory --- 2020-10-13 Bin Meng New
hw/intc: Move sifive_plic.h to the include directory hw/intc: Move sifive_plic.h to the include directory --- 2020-10-13 Bin Meng Superseded
[11/12] hw/riscv: Drop CONFIG_SIFIVE Untitled series #57815 --- 2020-09-03 Bin Meng New
[10/12] hw/riscv: Always build riscv_hart.c Untitled series #57815 --- 2020-09-03 Bin Meng New
[07/12] hw/riscv: Move riscv_htif model to hw/char Untitled series #57815 --- 2020-09-03 Bin Meng New
[04/12] hw/riscv: Move sifive_gpio model to hw/gpio Untitled series #57815 --- 2020-09-03 Bin Meng New
[03/12] hw/riscv: Move sifive_u_otp model to hw/misc Untitled series #57815 --- 2020-09-03 Bin Meng New
[02/12] hw/riscv: Move sifive_u_prci model to hw/misc Untitled series #57815 --- 2020-09-03 Bin Meng New
[v3,16/16] hw/riscv: sifive_u: Connect a DMA controller [v3,01/16] target/riscv: cpu: Add a new 'resetvec' property --- 2020-09-01 Bin Meng New
[v3,13/16] hw/riscv: microchip_pfsoc: Connect 2 Cadence GEMs [v3,01/16] target/riscv: cpu: Add a new 'resetvec' property --- 2020-09-01 Bin Meng Superseded
[v3,12/16] hw/arm: xlnx: Set all boards' GEM 'phy-addr' property value to 23 [v3,01/16] target/riscv: cpu: Add a new 'resetvec' property --- 2020-09-01 Bin Meng Superseded
[v3,09/16] hw/dma: Add SiFive platform DMA controller emulation [v3,01/16] target/riscv: cpu: Add a new 'resetvec' property --- 2020-09-01 Bin Meng Superseded
[v3,06/16] hw/riscv: microchip_pfsoc: Connect 5 MMUARTs [v3,01/16] target/riscv: cpu: Add a new 'resetvec' property --- 2020-09-01 Bin Meng New
[v3,05/16] hw/char: Add Microchip PolarFire SoC MMUART emulation [v3,01/16] target/riscv: cpu: Add a new 'resetvec' property --- 2020-09-01 Bin Meng Superseded
[v3,02/16] hw/riscv: hart: Add a new 'resetvec' property [v3,01/16] target/riscv: cpu: Add a new 'resetvec' property --- 2020-09-01 Bin Meng New
[v3,01/16] target/riscv: cpu: Add a new 'resetvec' property [v3,01/16] target/riscv: cpu: Add a new 'resetvec' property --- 2020-09-01 Bin Meng Superseded
[v2,14/16] hw/riscv: microchip_pfsoc: Hook GPIO controllers hw/riscv: Add Microchip PolarFire SoC Icicle Kit board support --- 2020-08-29 Bin Meng New
[v2,13/16] hw/riscv: microchip_pfsoc: Connect 2 Cadence GEMs hw/riscv: Add Microchip PolarFire SoC Icicle Kit board support --- 2020-08-29 Bin Meng New
[v2,12/16] hw/arm: xlnx: Set all boards' GEM 'phy-addr' property value to 23 hw/riscv: Add Microchip PolarFire SoC Icicle Kit board support --- 2020-08-29 Bin Meng New
[v2,09/16] hw/dma: Add SiFive platform DMA controller emulation hw/riscv: Add Microchip PolarFire SoC Icicle Kit board support --- 2020-08-29 Bin Meng New
[v2,08/16] hw/riscv: microchip_pfsoc: Connect a Cadence SDHCI controller and an SD card hw/riscv: Add Microchip PolarFire SoC Icicle Kit board support --- 2020-08-29 Bin Meng New
[v2,05/16] hw/char: Add Microchip PolarFire SoC MMUART emulation hw/riscv: Add Microchip PolarFire SoC Icicle Kit board support --- 2020-08-29 Bin Meng New
[v2,03/16] target/riscv: cpu: Set reset vector based on the configured property value hw/riscv: Add Microchip PolarFire SoC Icicle Kit board support --- 2020-08-29 Bin Meng New
[v2,01/16] target/riscv: cpu: Add a new 'resetvec' property hw/riscv: Add Microchip PolarFire SoC Icicle Kit board support --- 2020-08-29 Bin Meng New
[v3,1/2] hw/sd: sd: Fix incorrect populated function switch status data structure [v3,1/2] hw/sd: sd: Fix incorrect populated function switch status data structure --- 2020-08-21 Bin Meng Superseded
[v2,1/3] hw/sd: sd: Fix incorrect populated function switch status data structure hw/sd: Add Cadence SDHCI emulation --- 2020-08-17 Bin Meng New
[16/18] hw/riscv: microchip_pfsoc: Hook GPIO controllers Untitled series #58400 --- 2020-08-14 Bin Meng New
[15/18] hw/riscv: microchip_pfsoc: Connect 2 Cadence GEMs Untitled series #58400 --- 2020-08-14 Bin Meng New
[14/18] hw/net: cadence_gem: Add a new 'phy-addr' property Untitled series #58400 --- 2020-08-14 Bin Meng New
[11/18] hw/riscv: microchip_pfsoc: Connect a Cadence SDHCI controller and an SD card Untitled series #58400 --- 2020-08-14 Bin Meng New
[10/18] hw/sd: Add Cadence SDHCI emulation Untitled series #58400 --- 2020-08-14 Bin Meng New
[09/18] hw/sd: sdhci: Make sdhci_poweron_reset() internal visible Untitled series #58400 --- 2020-08-14 Bin Meng New
[08/18] hw/sd: sd: Correctly set the high capacity bit Untitled series #58400 --- 2020-08-14 Bin Meng New
[06/18] hw/riscv: microchip_pfsoc: Connect 5 MMUARTs Untitled series #58400 --- 2020-08-14 Bin Meng New
[04/18] hw/riscv: Initial support for Microchip PolarFire SoC Icicle Kit board Untitled series #58400 --- 2020-08-14 Bin Meng New
[02/18] hw/riscv: hart: Add a new 'resetvec' property Untitled series #58400 --- 2020-08-14 Bin Meng New
[v6,6/6] gitlab-ci/opensbi: Update GitLab CI to build generic platform riscv: Switch to use generic platform fw_dynamic type opensbi bios images --- 2020-08-03 Bin Meng Superseded
[v6,5/6] hw/riscv: spike: Change the default bios to use generic platform image riscv: Switch to use generic platform fw_dynamic type opensbi bios images --- 2020-08-03 Bin Meng New
[v6,2/6] roms/opensbi: Upgrade from v0.7 to v0.8 riscv: Switch to use generic platform fw_dynamic type opensbi bios images --- 2020-08-03 Bin Meng Superseded
hw/riscv: sifive_e: Correct debug block size hw/riscv: sifive_e: Correct debug block size --- 2020-07-16 Bin Meng New
[v5,7/7] Makefile: Ship the generic platform bios ELF images for RISC-V [v5,1/7] configure: Create symbolic links for pc-bios/*.elf files --- 2020-07-16 Bin Meng New
[v5,5/7] hw/riscv: spike: Change the default bios to use generic platform image [v5,1/7] configure: Create symbolic links for pc-bios/*.elf files --- 2020-07-16 Bin Meng Superseded
[v5,2/7] roms/opensbi: Upgrade from v0.7 to v0.8 [v5,1/7] configure: Create symbolic links for pc-bios/*.elf files --- 2020-07-16 Bin Meng Superseded
[v5,1/7] configure: Create symbolic links for pc-bios/*.elf files [v5,1/7] configure: Create symbolic links for pc-bios/*.elf files --- 2020-07-16 Bin Meng Superseded
[v4,6/7] gitlab-ci/opensbi: Update GitLab CI to build generic platform [v4,1/7] configure: Create symbolic links for pc-bios/*.elf files --- 2020-07-10 Bin Meng New
[v4,5/7] hw/riscv: spike: Change the default bios to use generic platform image [v4,1/7] configure: Create symbolic links for pc-bios/*.elf files --- 2020-07-10 Bin Meng New
[v4,4/7] hw/riscv: Use pre-built bios image of generic platform for virt & sifive_u [v4,1/7] configure: Create symbolic links for pc-bios/*.elf files --- 2020-07-10 Bin Meng New
[v4,1/7] configure: Create symbolic links for pc-bios/*.elf files [v4,1/7] configure: Create symbolic links for pc-bios/*.elf files --- 2020-07-10 Bin Meng Superseded
[v2,2/2] hw/riscv: sifive_u: Provide a reliable way for bootloader to detect whether it is running in QEMU Untitled series #59080 --- 2020-07-09 Bin Meng New
[2/2] hw/riscv: sifive_u: Provide a reliable way for bootloader to detect whether it is running in QEMU Untitled series #59087 --- 2020-07-09 Bin Meng New
hw/riscv: virt: Sort the SoC memmap table entries hw/riscv: virt: Sort the SoC memmap table entries --- 2020-07-03 Bin Meng New
[v3,4/7] hw/riscv: Use pre-built bios image of generic platform for virt & sifive_u riscv: Switch to use generic platform fw_dynamic type opensbi bios images --- 2020-07-03 Bin Meng New
[v3,2/7] roms/opensbi: Upgrade from v0.7 to v0.8 riscv: Switch to use generic platform fw_dynamic type opensbi bios images --- 2020-07-03 Bin Meng Superseded
[v3,1/7] configure: Create symbolic links for pc-bios/*.elf files riscv: Switch to use generic platform fw_dynamic type opensbi bios images --- 2020-07-03 Bin Meng Superseded
MAINTAINERS: Add an entry for OpenSBI firmware MAINTAINERS: Add an entry for OpenSBI firmware --- 2020-06-26 Bin Meng New
[v2,7/7] Makefile: Ship the generic platform bios images for RISC-V [v2,1/7] configure: Create symbolic links for pc-bios/*.elf files --- 2020-06-22 Bin Meng New
[v2,3/7] roms/Makefile: Build the generic platform for RISC-V OpenSBI firmware [v2,1/7] configure: Create symbolic links for pc-bios/*.elf files --- 2020-06-22 Bin Meng New
[v2,2/7] roms/opensbi: Upgrade from v0.7 to v0.8 [v2,1/7] configure: Create symbolic links for pc-bios/*.elf files --- 2020-06-22 Bin Meng New
[v2,1/7] configure: Create symbolic links for pc-bios/*.elf files [v2,1/7] configure: Create symbolic links for pc-bios/*.elf files --- 2020-06-22 Bin Meng New
[v2,3/5] hw/riscv: sifive_u: Support different boot source per MSEL pin state [v2,1/5] target/riscv: Rename IBEX CPU init routine --- 2020-06-16 Bin Meng Superseded
[v2,2/5] hw/riscv: sifive: Change SiFive E/U CPU reset vector to 0x1004 [v2,1/5] target/riscv: Rename IBEX CPU init routine --- 2020-06-16 Bin Meng New
[v2,1/5] target/riscv: Rename IBEX CPU init routine [v2,1/5] target/riscv: Rename IBEX CPU init routine --- 2020-06-16 Bin Meng New
[v2,3/4] riscv: Generalize CPU init routine for the imacu CPU [v2,1/4] riscv: Generalize CPU init routine for the base CPU --- 2020-06-11 Bin Meng New
[v2,1/4] riscv: Generalize CPU init routine for the base CPU [v2,1/4] riscv: Generalize CPU init routine for the base CPU --- 2020-06-11 Bin Meng Superseded
[13/15] hw/riscv: sifive_u: Support different boot source per MSEL pin state Untitled series #60036 --- 2020-06-08 Bin Meng New
[12/15] hw/riscv: sifive: Change SiFive E/U CPU reset vector to 0x1004 Untitled series #60036 --- 2020-06-08 Bin Meng New
[09/15] hw/riscv: sifive_u: Add reset functionality Untitled series #60036 --- 2020-06-08 Bin Meng New
[07/15] hw/riscv: sifive_u: Hook a GPIO controller Untitled series #60036 --- 2020-06-08 Bin Meng New
[06/15] hw/riscv: sifive_gpio: Add a new 'ngpio' property Untitled series #60036 --- 2020-06-08 Bin Meng New
[04/15] hw/riscv: sifive_u: Generate device tree node for OTP Untitled series #60036 --- 2020-06-08 Bin Meng New
[03/15] hw/riscv: sifive_u: Simplify the GEM IRQ connect code a little bit Untitled series #60036 --- 2020-06-08 Bin Meng New
[02/15] hw/riscv: opentitan: Remove the riscv_ prefix of the machine* and soc* functions Untitled series #60036 --- 2020-06-08 Bin Meng New
[1/4] riscv: Generalize CPU init routine for the base CPU [1/4] riscv: Generalize CPU init routine for the base CPU --- 2020-06-05 Bin Meng New
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