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[1/9] target/arm: Add M profile secure MMU index values to get_a32_user_mem_index()

Message ID 1507556919-24992-2-git-send-email-peter.maydell@linaro.org
State Superseded
Headers show
Series v8M: BLXNS, SG, secure function return | expand

Commit Message

Peter Maydell Oct. 9, 2017, 1:48 p.m. UTC 
Add the M profile secure MMU index values to the switch in
get_a32_user_mem_index() so that LDRT/STRT work correctly
rather than asserting at translate time.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

---
 target/arm/translate.c | 4 ++++
 1 file changed, 4 insertions(+)

-- 
2.7.4

Comments

Richard Henderson Oct. 10, 2017, 11:36 p.m. UTC | #1 
On 10/09/2017 06:48 AM, Peter Maydell wrote:
> Add the M profile secure MMU index values to the switch in

> get_a32_user_mem_index() so that LDRT/STRT work correctly

> rather than asserting at translate time.

> 

> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

> ---

>  target/arm/translate.c | 4 ++++

>  1 file changed, 4 insertions(+)


Reviewed-by: Richard Henderson <richard.henderson@linaro.org>



r~
diff mbox series

Patch

diff --git a/target/arm/translate.c b/target/arm/translate.c
index ab1a12a..e1b83b7 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -165,6 +165,10 @@  static inline int get_a32_user_mem_index(DisasContext *s)
     case ARMMMUIdx_MPriv:
     case ARMMMUIdx_MNegPri:
         return arm_to_core_mmu_idx(ARMMMUIdx_MUser);
+    case ARMMMUIdx_MSUser:
+    case ARMMMUIdx_MSPriv:
+    case ARMMMUIdx_MSNegPri:
+        return arm_to_core_mmu_idx(ARMMMUIdx_MSUser);
     case ARMMMUIdx_S2NS:
     default:
         g_assert_not_reached();