Show patches with: Series = target-arm queue       |    Archived = No       |   48 patches
Patch Series S/W/F Date Submitter Delegate State
[PULL,48/48] target/arm: Fix short-vector increment behaviour target-arm queue --- 2019-06-13 Peter Maydell Not Applicable
[PULL,47/48] target/arm: Convert float-to-integer VCVT insns to decodetree target-arm queue --- 2019-06-13 Peter Maydell Accepted
[PULL,46/48] target/arm: Convert VCVT fp/fixed-point conversion insns to decodetree target-arm queue --- 2019-06-13 Peter Maydell Accepted
[PULL,45/48] target/arm: Convert VJCVT to decodetree target-arm queue --- 2019-06-13 Peter Maydell Accepted
[PULL,44/48] target/arm: Convert integer-to-float insns to decodetree target-arm queue --- 2019-06-13 Peter Maydell Accepted
[PULL,43/48] target/arm: Convert double-single precision conversion insns to decodetree target-arm queue --- 2019-06-13 Peter Maydell Accepted
[PULL,42/48] target/arm: Convert VFP round insns to decodetree target-arm queue --- 2019-06-13 Peter Maydell Accepted
[PULL,41/48] target/arm: Convert the VCVT-to-f16 insns to decodetree target-arm queue --- 2019-06-13 Peter Maydell Accepted
[PULL,40/48] target/arm: Convert the VCVT-from-f16 insns to decodetree target-arm queue --- 2019-06-13 Peter Maydell Accepted
[PULL,39/48] target/arm: Convert VFP comparison insns to decodetree target-arm queue --- 2019-06-13 Peter Maydell Accepted
[PULL,38/48] target/arm: Convert VMOV (register) to decodetree target-arm queue --- 2019-06-13 Peter Maydell Accepted
[PULL,37/48] target/arm: Convert VSQRT to decodetree target-arm queue --- 2019-06-13 Peter Maydell Accepted
[PULL,36/48] target/arm: Convert VNEG to decodetree target-arm queue --- 2019-06-13 Peter Maydell Accepted
[PULL,35/48] target/arm: Convert VABS to decodetree target-arm queue --- 2019-06-13 Peter Maydell Not Applicable
[PULL,34/48] target/arm: Convert VMOV (imm) to decodetree target-arm queue --- 2019-06-13 Peter Maydell Accepted
[PULL,33/48] target/arm: Convert VFP fused multiply-add insns to decodetree target-arm queue --- 2019-06-13 Peter Maydell Accepted
[PULL,32/48] target/arm: Convert VDIV to decodetree target-arm queue --- 2019-06-13 Peter Maydell Accepted
[PULL,31/48] target/arm: Convert VSUB to decodetree target-arm queue --- 2019-06-13 Peter Maydell Accepted
[PULL,30/48] target/arm: Convert VADD to decodetree target-arm queue --- 2019-06-13 Peter Maydell Accepted
[PULL,29/48] target/arm: Convert VNMUL to decodetree target-arm queue --- 2019-06-13 Peter Maydell Accepted
[PULL,28/48] target/arm: Convert VMUL to decodetree target-arm queue --- 2019-06-13 Peter Maydell Accepted
[PULL,27/48] target/arm: Convert VFP VNMLA to decodetree target-arm queue --- 2019-06-13 Peter Maydell Accepted
[PULL,26/48] target/arm: Convert VFP VNMLS to decodetree target-arm queue --- 2019-06-13 Peter Maydell Accepted
[PULL,25/48] target/arm: Convert VFP VMLS to decodetree target-arm queue --- 2019-06-13 Peter Maydell Accepted
[PULL,24/48] target/arm: Convert VFP VMLA to decodetree target-arm queue --- 2019-06-13 Peter Maydell Accepted
[PULL,23/48] target/arm: Remove VLDR/VSTR/VLDM/VSTM use of cpu_F0s and cpu_F0d target-arm queue --- 2019-06-13 Peter Maydell Not Applicable
[PULL,22/48] target/arm: Convert the VFP load/store multiple insns to decodetree target-arm queue --- 2019-06-13 Peter Maydell Accepted
[PULL,21/48] target/arm: Convert VFP VLDR and VSTR to decodetree target-arm queue --- 2019-06-13 Peter Maydell Accepted
[PULL,20/48] target/arm: Convert VFP two-register transfer insns to decodetree target-arm queue --- 2019-06-13 Peter Maydell Accepted
[PULL,19/48] target/arm: Convert "single-precision" register moves to decodetree target-arm queue --- 2019-06-13 Peter Maydell Accepted
[PULL,18/48] target/arm: Convert "double-precision" register moves to decodetree target-arm queue --- 2019-06-13 Peter Maydell Accepted
[PULL,17/48] target/arm: Add helpers for VFP register loads and stores target-arm queue --- 2019-06-13 Peter Maydell Accepted
[PULL,16/48] target/arm: Move the VFP trans_* functions to translate-vfp.inc.c target-arm queue --- 2019-06-13 Peter Maydell Accepted
[PULL,15/48] target/arm: Convert VCVTA/VCVTN/VCVTP/VCVTM to decodetree target-arm queue --- 2019-06-13 Peter Maydell Accepted
[PULL,14/48] target/arm: Convert VRINTA/VRINTN/VRINTP/VRINTM to decodetree target-arm queue --- 2019-06-13 Peter Maydell Accepted
[PULL,13/48] target/arm: Convert VMINNM, VMAXNM to decodetree target-arm queue --- 2019-06-13 Peter Maydell Accepted
[PULL,12/48] target/arm: Convert the VSEL instructions to decodetree target-arm queue --- 2019-06-13 Peter Maydell Accepted
[PULL,11/48] target/arm: Explicitly enable VFP short-vectors for aarch32 -cpu max target-arm queue --- 2019-06-13 Peter Maydell Accepted
[PULL,10/48] target/arm: Fix Cortex-R5F MVFR values target-arm queue --- 2019-06-13 Peter Maydell Not Applicable
[PULL,09/48] target/arm: Factor out VFP access checking code target-arm queue --- 2019-06-13 Peter Maydell Accepted
[PULL,08/48] target/arm: Add stubs for AArch32 VFP decodetree target-arm queue --- 2019-06-13 Peter Maydell Accepted
[PULL,07/48] decodetree: Fix comparison of Field target-arm queue --- 2019-06-13 Peter Maydell Accepted
[PULL,06/48] target/arm: Fix output of PAuth Auth target-arm queue --- 2019-06-13 Peter Maydell Not Applicable
[PULL,05/48] hw/core/bus.c: Only the main system bus can have no parent target-arm queue --- 2019-06-13 Peter Maydell Accepted
[PULL,04/48] hw/arm/smmuv3: Fix decoding of ID register range target-arm queue --- 2019-06-13 Peter Maydell Accepted
[PULL,03/48] target/arm: Implement NSACR gating of floating point target-arm queue --- 2019-06-13 Peter Maydell Accepted
[PULL,02/48] target/arm: Use tcg_gen_gvec_bitsel target-arm queue --- 2019-06-13 Peter Maydell Not Applicable
[PULL,01/48] target/arm: Vectorize USHL and SSHL target-arm queue --- 2019-06-13 Peter Maydell Superseded